X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fexecute.cc;h=9d1fb87ad2da6a8cccca13eb3f01e5ff61147ac4;hb=1da69b975beeda193d5fa47950be5883ca20ad13;hp=e60ffd117ebeb58a0f8f16c46bb5161ce1d58053;hpb=dfa7a56754c8362c9d183c4f0e16843124221669;p=riscv-isa-sim.git

diff --git a/riscv/execute.cc b/riscv/execute.cc
index e60ffd1..9d1fb87 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -2,7 +2,6 @@
 
 #include "processor.h"
 #include "mmu.h"
-#include "sim.h"
 #include <cassert>
 
 
@@ -128,6 +127,13 @@ void processor_t::step(size_t n)
       {
         while (instret < n)
         {
+          if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) {
+            state.single_step = state.STEP_NONE;
+            enter_debug_mode(DCSR_CAUSE_STEP);
+            // enter_debug_mode changed state.pc, so we can't just continue.
+            break;
+          }
+
           if (unlikely(state.single_step == state.STEP_STEPPING)) {
             state.single_step = state.STEP_STEPPED;
           }
@@ -136,17 +142,9 @@ void processor_t::step(size_t n)
           if (debug && !state.serialized)
             disasm(fetch.insn);
           pc = execute_insn(this, pc, fetch);
-          bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
 
           advance_pc();
 
-          if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
-            state.single_step = state.STEP_NONE;
-            enter_debug_mode(DCSR_CAUSE_STEP);
-            // enter_debug_mode changed state.pc, so we can't just continue.
-            break;
-          }
-
           if (unlikely(state.pc >= DEBUG_ROM_ENTRY &&
                        state.pc < DEBUG_END)) {
             // We're waiting for the debugger to tell us something.