X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Fc_fsw.h;h=b924a4689dc58dc4b0e7352c135d5eecefbac6d2;hb=d6fce459767509249311a120fddb21c844dc9b2c;hp=8923fef38fb1a5f88780cb1d893736809126b16a;hpb=5f494a22db29d69893db4b39f488cf67c0ac6437;p=riscv-isa-sim.git

diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index 8923fef..b924a46 100644
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S);
+  MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v);
 } else { // c.sd
   MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
 }