X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Fc_lw.h;h=ef49dd90904f1608b9a5320cb8ccd17228020ee1;hb=bdcb5b297f9919bdd1a1b6031a3b5c469e982d14;hp=f2fc2991d32a0fe5925cf048c8a6bf9fb0892605;hpb=292fef830dad9d6d8b868ba27cf4ddd80bf9243a;p=riscv-isa-sim.git

diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h
index f2fc299..ef49dd9 100644
--- a/riscv/insns/c_lw.h
+++ b/riscv/insns/c_lw.h
@@ -1,2 +1,2 @@
 require_extension('C');
-WRITE_RVC_RDS(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));
+WRITE_RVC_RS2S(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));