X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Fc_lw.h;h=f2fc2991d32a0fe5925cf048c8a6bf9fb0892605;hb=c4350ef6ef6259e48509e125fd2d051969dc6efa;hp=9c6f470cd23ec1137ba78cfb826e27b65dff870e;hpb=d9d73d80c1b738b3b30eb40d192f61cbdb0e201f;p=riscv-isa-sim.git

diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h
index 9c6f470..f2fc299 100644
--- a/riscv/insns/c_lw.h
+++ b/riscv/insns/c_lw.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RVC_RDS(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));