X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Fc_lwsp.h;h=b3d74dbf087fb09553ca438bf4c44629ecfdc032;hb=bdcb5b297f9919bdd1a1b6031a3b5c469e982d14;hp=ed4dcf30887e4e299fd2cff5835a4faf521dc3e5;hpb=292fef830dad9d6d8b868ba27cf4ddd80bf9243a;p=riscv-isa-sim.git

diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h
index ed4dcf3..b3d74db 100644
--- a/riscv/insns/c_lwsp.h
+++ b/riscv/insns/c_lwsp.h
@@ -1,2 +1,3 @@
 require_extension('C');
+require(insn.rvc_rd() != 0);
 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));