X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Fc_lwsp.h;h=ed4dcf30887e4e299fd2cff5835a4faf521dc3e5;hb=c4350ef6ef6259e48509e125fd2d051969dc6efa;hp=8d9b9e3bf845326187998905ab39c11db1597bb3;hpb=d9d73d80c1b738b3b30eb40d192f61cbdb0e201f;p=riscv-isa-sim.git

diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h
index 8d9b9e3..ed4dcf3 100644
--- a/riscv/insns/c_lwsp.h
+++ b/riscv/insns/c_lwsp.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));