X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Fc_sw.h;h=3073e9d623dcb98265b2c1d1d3c59f51530ab386;hb=c4350ef6ef6259e48509e125fd2d051969dc6efa;hp=34deb9dc0c309ecef06814b8aeee884f12ae45e1;hpb=d9d73d80c1b738b3b30eb40d192f61cbdb0e201f;p=riscv-isa-sim.git

diff --git a/riscv/insns/c_sw.h b/riscv/insns/c_sw.h
index 34deb9d..3073e9d 100644
--- a/riscv/insns/c_sw.h
+++ b/riscv/insns/c_sw.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_RS2S);