X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Fc_swsp.h;h=6f3fef0dcdf15855f30a3a3e4a35ee5c6d4e7182;hb=c4350ef6ef6259e48509e125fd2d051969dc6efa;hp=bbb5ad058b598f43691637772dab4a4c9b479e63;hpb=d9d73d80c1b738b3b30eb40d192f61cbdb0e201f;p=riscv-isa-sim.git

diff --git a/riscv/insns/c_swsp.h b/riscv/insns/c_swsp.h
index bbb5ad0..6f3fef0 100644
--- a/riscv/insns/c_swsp.h
+++ b/riscv/insns/c_swsp.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 MMU.store_uint32(RVC_SP + insn.rvc_lwsp_imm(), RVC_RS2);