X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Ffcvt_d_s.h;h=5f805b061472c89dabdb25af51fb69a3fe1eefa1;hb=d6fce459767509249311a120fddb21c844dc9b2c;hp=ec778cc92f475446212fca675014dff066076b26;hpb=5f494a22db29d69893db4b39f488cf67c0ac6437;p=riscv-isa-sim.git

diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h
index ec778cc..5f805b0 100644
--- a/riscv/insns/fcvt_d_s.h
+++ b/riscv/insns/fcvt_d_s.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_to_f64(f32(FRS1)).v);
+WRITE_FRD(f32_to_f64(f32(FRS1)));
 set_fp_exceptions;