X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Ffcvt_s_wu.h;h=c1394c3fd04af3f078f9cd29d201a52c63e199e4;hb=d6fce459767509249311a120fddb21c844dc9b2c;hp=a6cf8367f99d5a1f15b6d0e10bfdf237e053443f;hpb=5f494a22db29d69893db4b39f488cf67c0ac6437;p=riscv-isa-sim.git

diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index a6cf836..c1394c3 100644
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f32((uint32_t)RS1).v);
+WRITE_FRD(ui32_to_f32((uint32_t)RS1));
 set_fp_exceptions;