X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Ffmsub_s.h;h=d46c887e7c746137aebe24e64880fadb3fa34fdb;hb=d6fce459767509249311a120fddb21c844dc9b2c;hp=45945dac4a48fd1230ddc5174e94a9915c896a24;hpb=5f494a22db29d69893db4b39f488cf67c0ac6437;p=riscv-isa-sim.git

diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index 45945da..d46c887 100644
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)).v);
+WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
 set_fp_exceptions;