X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Ffsw.h;h=3135e9b7dace76cc7866b46d6415965ade82a84f;hb=c4350ef6ef6259e48509e125fd2d051969dc6efa;hp=85c8091ab16af0a2c8d15f86310dc2b5ee27fb98;hpb=d9d73d80c1b738b3b30eb40d192f61cbdb0e201f;p=riscv-isa-sim.git

diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 85c8091..3135e9b 100644
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 MMU.store_uint32(RS1 + insn.s_imm(), FRS2);