X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finsns%2Flr_w.h;h=767251f9e07775dfe2edc01b726f1f661e43feb5;hb=c4350ef6ef6259e48509e125fd2d051969dc6efa;hp=2b954195b79b9eca3ca5289b1b1efaf0db6880c5;hpb=d9d73d80c1b738b3b30eb40d192f61cbdb0e201f;p=riscv-isa-sim.git

diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h
index 2b95419..767251f 100644
--- a/riscv/insns/lr_w.h
+++ b/riscv/insns/lr_w.h
@@ -1,2 +1,3 @@
+require_extension('A');
 p->get_state()->load_reservation = RS1;
 WRITE_RD(MMU.load_int32(RS1));