X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finteractive.cc;h=dbcd22455d5fe6fdb75388946df176d7227ca6df;hb=a91d9f7d89abd6cda6fafb7b5e7cacf4b3590c29;hp=c4eb869d6c47462db98ca105a5aef91465c0439d;hpb=89be91cec3677f3f1143972de7ca85e2dc33dbff;p=riscv-isa-sim.git

diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index c4eb869..dbcd224 100644
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -3,7 +3,7 @@
 #include "decode.h"
 #include "disasm.h"
 #include "sim.h"
-#include "htif.h"
+#include "mmu.h"
 #include <sys/mman.h>
 #include <termios.h>
 #include <map>
@@ -17,13 +17,16 @@
 #include <string>
 #include <vector>
 #include <algorithm>
+#include <math.h>
+
+DECLARE_TRAP(-1, interactive)
 
 processor_t *sim_t::get_core(const std::string& i)
 {
   char *ptr;
   unsigned long p = strtoul(i.c_str(), &ptr, 10);
-  if (*ptr || p >= num_cores())
-    throw trap_illegal_instruction();
+  if (*ptr || p >= procs.size())
+    throw trap_interactive();
   return get_core(p);
 }
 
@@ -64,8 +67,10 @@ void sim_t::interactive()
   funcs["r"] = funcs["run"];
   funcs["rs"] = &sim_t::interactive_run_silent;
   funcs["reg"] = &sim_t::interactive_reg;
+  funcs["freg"] = &sim_t::interactive_freg;
   funcs["fregs"] = &sim_t::interactive_fregs;
   funcs["fregd"] = &sim_t::interactive_fregd;
+  funcs["pc"] = &sim_t::interactive_pc;
   funcs["mem"] = &sim_t::interactive_mem;
   funcs["str"] = &sim_t::interactive_str;
   funcs["until"] = &sim_t::interactive_until;
@@ -75,7 +80,7 @@ void sim_t::interactive()
   funcs["help"] = &sim_t::interactive_help;
   funcs["h"] = funcs["help"];
 
-  while (!htif->done())
+  while (!done())
   {
     std::cerr << ": " << std::flush;
     std::string s = readline(2);
@@ -98,6 +103,8 @@ void sim_t::interactive()
     {
       if(funcs.count(cmd))
         (this->*funcs[cmd])(cmd, args);
+      else
+        fprintf(stderr, "Unknown command %s\n", cmd.c_str());
     }
     catch(trap_t t) {}
   }
@@ -108,9 +115,10 @@ void sim_t::interactive_help(const std::string& cmd, const std::vector<std::stri
 {
   std::cerr <<
     "Interactive commands:\n"
-    "reg <core> <reg>                # Display <reg> in <core>\n"
+    "reg <core> [reg]                # Display [reg] (all if omitted) in <core>\n"
     "fregs <core> <reg>              # Display single precision <reg> in <core>\n"
     "fregd <core> <reg>              # Display double precision <reg> in <core>\n"
+    "pc <core>                       # Show current PC in <core>\n"
     "mem <hex addr>                  # Show contents of physical memory\n"
     "str <hex addr>                  # Show NUL-terminated C string\n"
     "until reg <core> <reg> <val>    # Stop when <reg> in <core> hits <val>\n"
@@ -145,7 +153,7 @@ void sim_t::interactive_run(const std::string& cmd, const std::vector<std::strin
   size_t steps = args.size() ? atoll(args[0].c_str()) : -1;
   ctrlc_pressed = false;
   set_procs_debug(noisy);
-  for (size_t i = 0; i < steps && !ctrlc_pressed && !htif->done(); i++)
+  for (size_t i = 0; i < steps && !ctrlc_pressed && !done(); i++)
     step(1);
 }
 
@@ -157,16 +165,21 @@ void sim_t::interactive_quit(const std::string& cmd, const std::vector<std::stri
 reg_t sim_t::get_pc(const std::vector<std::string>& args)
 {
   if(args.size() != 1)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   processor_t *p = get_core(args[0]);
   return p->state.pc;
 }
 
+void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string>& args)
+{
+  fprintf(stderr, "0x%016" PRIx64 "\n", get_pc(args));
+}
+
 reg_t sim_t::get_reg(const std::vector<std::string>& args)
 {
   if(args.size() != 2)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   processor_t *p = get_core(args[0]);
 
@@ -176,64 +189,79 @@ reg_t sim_t::get_reg(const std::vector<std::string>& args)
     r = strtoul(args[1].c_str(), &ptr, 10);
     if (*ptr) {
       #define DECLARE_CSR(name, number) if (args[1] == #name) return p->get_csr(number);
-      if (0) ;
-      #include "encoding.h"
-      else r = NXPR;
+      #include "encoding.h"              // generates if's for all csrs
+      r = NXPR;                          // else case (csr name not found)
       #undef DECLARE_CSR
     }
   }
 
   if (r >= NXPR)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   return p->state.XPR[r];
 }
 
-reg_t sim_t::get_freg(const std::vector<std::string>& args)
+freg_t sim_t::get_freg(const std::vector<std::string>& args)
 {
   if(args.size() != 2)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   processor_t *p = get_core(args[0]);
   int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name;
   if (r == NFPR)
     r = atoi(args[1].c_str());
   if (r >= NFPR)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   return p->state.FPR[r];
 }
 
 void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args)
 {
-  fprintf(stderr, "0x%016" PRIx64 "\n", get_reg(args));
+  if (args.size() == 1) {
+    // Show all the regs!
+    processor_t *p = get_core(args[0]);
+
+    for (int r = 0; r < NXPR; ++r) {
+      fprintf(stderr, "%-4s: 0x%016" PRIx64 "  ", xpr_name[r], p->state.XPR[r]);
+      if ((r + 1) % 4 == 0)
+        fprintf(stderr, "\n");
+    }
+  } else
+    fprintf(stderr, "0x%016" PRIx64 "\n", get_reg(args));
 }
 
 union fpr
 {
-  reg_t r;
+  freg_t r;
   float s;
   double d;
 };
 
+void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::string>& args)
+{
+  freg_t r = get_freg(args);
+  fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64 "\n", r.v[1], r.v[0]);
+}
+
 void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
 {
   fpr f;
   f.r = get_freg(args);
-  fprintf(stderr, "%g\n",f.s);
+  fprintf(stderr, "%g\n", isBoxedF32(f.r) ? (double)f.s : NAN);
 }
 
 void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args)
 {
   fpr f;
   f.r = get_freg(args);
-  fprintf(stderr, "%g\n",f.d);
+  fprintf(stderr, "%g\n", isBoxedF64(f.r) ? f.d : NAN);
 }
 
 reg_t sim_t::get_mem(const std::vector<std::string>& args)
 {
   if(args.size() != 1 && args.size() != 2)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   std::string addr_str = args[0];
   mmu_t* mmu = debug_mmu;
@@ -275,7 +303,7 @@ void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::strin
 void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args)
 {
   if(args.size() != 1)
-    throw trap_illegal_instruction();
+    throw trap_interactive();
 
   reg_t addr = strtol(args[0].c_str(),NULL,16);