X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Finteractive.cc;h=dbcd22455d5fe6fdb75388946df176d7227ca6df;hb=a91d9f7d89abd6cda6fafb7b5e7cacf4b3590c29;hp=ee8837522e163649268e3f74e4fb80c941420fd5;hpb=4c80b12b1a96fee64bfbdd35d097d867599eee1e;p=riscv-isa-sim.git diff --git a/riscv/interactive.cc b/riscv/interactive.cc index ee88375..dbcd224 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -17,6 +17,7 @@ #include #include #include +#include DECLARE_TRAP(-1, interactive) @@ -66,6 +67,7 @@ void sim_t::interactive() funcs["r"] = funcs["run"]; funcs["rs"] = &sim_t::interactive_run_silent; funcs["reg"] = &sim_t::interactive_reg; + funcs["freg"] = &sim_t::interactive_freg; funcs["fregs"] = &sim_t::interactive_fregs; funcs["fregd"] = &sim_t::interactive_fregd; funcs["pc"] = &sim_t::interactive_pc; @@ -199,7 +201,7 @@ reg_t sim_t::get_reg(const std::vector& args) return p->state.XPR[r]; } -reg_t sim_t::get_freg(const std::vector& args) +freg_t sim_t::get_freg(const std::vector& args) { if(args.size() != 2) throw trap_interactive(); @@ -231,23 +233,29 @@ void sim_t::interactive_reg(const std::string& cmd, const std::vector& args) +{ + freg_t r = get_freg(args); + fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64 "\n", r.v[1], r.v[0]); +} + void sim_t::interactive_fregs(const std::string& cmd, const std::vector& args) { fpr f; f.r = get_freg(args); - fprintf(stderr, "%g\n",f.s); + fprintf(stderr, "%g\n", isBoxedF32(f.r) ? (double)f.s : NAN); } void sim_t::interactive_fregd(const std::string& cmd, const std::vector& args) { fpr f; f.r = get_freg(args); - fprintf(stderr, "%g\n",f.d); + fprintf(stderr, "%g\n", isBoxedF64(f.r) ? f.d : NAN); } reg_t sim_t::get_mem(const std::vector& args)