X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fjtag_dtm.cc;h=365528a49a7566919c7b0742151f3fab846b5435;hb=aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e;hp=3750f9db8a9c472a3d74bbfd425d2a304f469080;hpb=f7f110504072dc601a24a4391cbf3b0091a47a12;p=riscv-isa-sim.git

diff --git a/riscv/jtag_dtm.cc b/riscv/jtag_dtm.cc
index 3750f9d..365528a 100644
--- a/riscv/jtag_dtm.cc
+++ b/riscv/jtag_dtm.cc
@@ -5,7 +5,7 @@
 #include "debug_module.h"
 #include "debug_defines.h"
 
-#if 1
+#if 0
 #  define D(x) x
 #else
 #  define D(x)
@@ -14,7 +14,8 @@
 enum {
   IR_IDCODE=1,
   IR_DTMCONTROL=0x10,
-  IR_DBUS=0x11
+  IR_DBUS=0x11,
+  IR_RESET=0x1c
 };
 
 #define DTMCONTROL_VERSION      0xf
@@ -23,31 +24,31 @@ enum {
 #define DTMCONTROL_IDLE         (7<<12)
 #define DTMCONTROL_DBUSRESET    (1<<16)
 
-#define DBUS_OP                 3
-#define DBUS_DATA               (0xffffffffL<<2)
-#define DBUS_ADDRESS            ((1L<<(abits+34)) - (1L<<34))
+#define DMI_OP                 3
+#define DMI_DATA               (0xffffffffL<<2)
+#define DMI_ADDRESS            ((1L<<(abits+34)) - (1L<<34))
 
-#define DBUS_OP_STATUS_SUCCESS	0
-#define DBUS_OP_STATUS_RESERVED	1
-#define DBUS_OP_STATUS_FAILED	2
-#define DBUS_OP_STATUS_BUSY	3
+#define DMI_OP_STATUS_SUCCESS	0
+#define DMI_OP_STATUS_RESERVED	1
+#define DMI_OP_STATUS_FAILED	2
+#define DMI_OP_STATUS_BUSY	3
 
-#define DBUS_OP_NOP	        0
-#define DBUS_OP_READ	        1
-#define DBUS_OP_READ_WRITE	2
-#define DBUS_OP_RESERVED	3
+#define DMI_OP_NOP	        0
+#define DMI_OP_READ	        1
+#define DMI_OP_WRITE	        2
+#define DMI_OP_RESERVED	        3
 
 jtag_dtm_t::jtag_dtm_t(debug_module_t *dm) :
   dm(dm),
   _tck(false), _tms(false), _tdi(false), _tdo(false),
-  dtmcontrol((abits << DTM_DTMCONTROL_ABITS_OFFSET) | 1),
-  dbus(DBUS_OP_STATUS_FAILED << DTM_DBUS_OP_OFFSET),
-  state(TEST_LOGIC_RESET)
+  dtmcontrol((abits << DTM_DTMCS_ABITS_OFFSET) | 1),
+  dmi(DMI_OP_STATUS_SUCCESS << DTM_DMI_OP_OFFSET),
+  _state(TEST_LOGIC_RESET)
 {
 }
 
 void jtag_dtm_t::reset() {
-  state = TEST_LOGIC_RESET;
+  _state = TEST_LOGIC_RESET;
 }
 
 void jtag_dtm_t::set_pins(bool tck, bool tms, bool tdi) {
@@ -73,7 +74,7 @@ void jtag_dtm_t::set_pins(bool tck, bool tms, bool tdi) {
   if (!_tck && tck) {
     // Positive clock edge.
 
-    switch (state) {
+    switch (_state) {
       case SHIFT_DR:
         dr >>= 1;
         dr |= (uint64_t) _tdi << (dr_length-1);
@@ -85,8 +86,8 @@ void jtag_dtm_t::set_pins(bool tck, bool tms, bool tdi) {
       default:
         break;
     }
-    state = next[state][_tms];
-    switch (state) {
+    _state = next[_state][_tms];
+    switch (_state) {
       case TEST_LOGIC_RESET:
         ir = IR_IDCODE;
         break;
@@ -104,18 +105,19 @@ void jtag_dtm_t::set_pins(bool tck, bool tms, bool tdi) {
       case SHIFT_IR:
         _tdo = ir & 1;
         break;
-      case UPDATE_IR:
-        break;
+      //case UPDATE_IR:
+        //if (ir == IR_RESET) {
+          // Make a reset happen
+        //}
+        //break;
       default:
         break;
     }
   }
 
-  /*
   D(fprintf(stderr, "state=%2d, tdi=%d, tdo=%d, tms=%d, tck=%d, ir=0x%02x, "
         "dr=0x%lx\n",
-        state, _tdi, _tdo, _tms, _tck, ir, dr));
-        */
+        _state, _tdi, _tdo, _tms, _tck, ir, dr));
 
   _tck = tck;
   _tms = tms;
@@ -134,7 +136,7 @@ void jtag_dtm_t::capture_dr()
       dr_length = 32;
       break;
     case IR_DBUS:
-      dr = dbus;
+      dr = dmi;
       dr_length = abits + 34;
       break;
     default:
@@ -152,31 +154,30 @@ void jtag_dtm_t::update_dr()
   switch (ir) {
     case IR_DBUS:
       {
-        unsigned op = get_field(dr, DBUS_OP);
-        uint32_t data = get_field(dr, DBUS_DATA);
-        unsigned address = get_field(dr, DBUS_ADDRESS);
+        unsigned op = get_field(dr, DMI_OP);
+        uint32_t data = get_field(dr, DMI_DATA);
+        unsigned address = get_field(dr, DMI_ADDRESS);
 
-        dbus = dr;
+        dmi = dr;
 
         bool success = true;
-        if (op == DBUS_OP_READ || op == DBUS_OP_READ_WRITE) {
+        if (op == DMI_OP_READ) {
           uint32_t value;
           if (dm->dmi_read(address, &value)) {
-            dbus = set_field(dbus, DBUS_DATA, value);
+            dmi = set_field(dmi, DMI_DATA, value);
           } else {
             success = false;
           }
-        }
-        if (success && op == DBUS_OP_READ_WRITE) {
+        } else if (op == DMI_OP_WRITE) {
           success = dm->dmi_write(address, data);
         }
 
         if (success) {
-          dbus = set_field(dbus, DBUS_OP, DBUS_OP_STATUS_SUCCESS);
+          dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_SUCCESS);
         } else {
-          dbus = set_field(dbus, DBUS_OP, DBUS_OP_STATUS_FAILED);
+          dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_FAILED);
         }
-        D(fprintf(stderr, "dbus=0x%lx\n", dbus));
+        D(fprintf(stderr, "dmi=0x%lx\n", dmi));
       }
       break;
   }