X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fmmu.cc;h=3a0bd39b89471470cef1155f201a646b673cbfab;hb=d6fcfdebf6a893bf37670fd67203d18653df4a0e;hp=489aeeee028a16a2bb8d8259ebe11e066217ccc5;hpb=069c07f440ac207a3bbe71f79c2834a9f0b919e5;p=riscv-isa-sim.git

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 489aeee..3a0bd39 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -1,10 +1,15 @@
+// See LICENSE for license details.
+
 #include "mmu.h"
-#include "sim.h"
+#include "simif.h"
 #include "processor.h"
 
-mmu_t::mmu_t(char* _mem, size_t _memsz)
- : mem(_mem), memsz(_memsz), badvaddr(0),
-   ptbr(0), supervisor(true), vm_enabled(false)
+mmu_t::mmu_t(simif_t* sim, processor_t* proc)
+ : sim(sim), proc(proc),
+  check_triggers_fetch(false),
+  check_triggers_load(false),
+  check_triggers_store(false),
+  matched_trigger(NULL)
 {
   flush_tlb();
 }
@@ -13,6 +18,12 @@ mmu_t::~mmu_t()
 {
 }
 
+void mmu_t::flush_icache()
+{
+  for (size_t i = 0; i < ICACHE_ENTRIES; i++)
+    icache[i].tag = -1;
+}
+
 void mmu_t::flush_tlb()
 {
   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
@@ -22,83 +33,208 @@ void mmu_t::flush_tlb()
   flush_icache();
 }
 
-void mmu_t::flush_icache()
+reg_t mmu_t::translate(reg_t addr, access_type type)
 {
-  memset(icache_tag, -1, sizeof(icache_tag));
+  if (!proc)
+    return addr;
+
+  reg_t mode = proc->state.prv;
+  if (type != FETCH) {
+    if (!proc->state.dcsr.cause && get_field(proc->state.mstatus, MSTATUS_MPRV))
+      mode = get_field(proc->state.mstatus, MSTATUS_MPP);
+  }
+
+  return walk(addr, type, mode) | (addr & (PGSIZE-1));
 }
 
-void* mmu_t::refill(reg_t addr, bool store, bool fetch)
+tlb_entry_t mmu_t::fetch_slow_path(reg_t vaddr)
 {
-  reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
-  reg_t expected_tag = addr & ~(PGSIZE-1);
-
-  reg_t pte = walk(addr);
-
-  reg_t pte_perm = pte & PTE_PERM;
-  if(supervisor) // shift supervisor permission bits into user perm bits
-    pte_perm = (pte_perm/(PTE_SX/PTE_UX)) & PTE_PERM;
-  pte_perm |= pte & PTE_E;
-
-  reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_E;
-  if(unlikely((pte_perm & perm) != perm))
-  {
-    badvaddr = addr;
-    throw store ? trap_store_access_fault
-        : fetch ? trap_instruction_access_fault
-        :         trap_load_access_fault;
+  reg_t paddr = translate(vaddr, FETCH);
+
+  if (auto host_addr = sim->addr_to_mem(paddr)) {
+    return refill_tlb(vaddr, paddr, host_addr, FETCH);
+  } else {
+    if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp))
+      throw trap_instruction_access_fault(vaddr);
+    tlb_entry_t entry = {(char*)&fetch_temp - vaddr, paddr - vaddr};
+    return entry;
   }
+}
+
+reg_t reg_from_bytes(size_t len, const uint8_t* bytes)
+{
+  switch (len) {
+    case 1:
+      return bytes[0];
+    case 2:
+      return bytes[0] |
+        (((reg_t) bytes[1]) << 8);
+    case 4:
+      return bytes[0] |
+        (((reg_t) bytes[1]) << 8) |
+        (((reg_t) bytes[2]) << 16) |
+        (((reg_t) bytes[3]) << 24);
+    case 8:
+      return bytes[0] |
+        (((reg_t) bytes[1]) << 8) |
+        (((reg_t) bytes[2]) << 16) |
+        (((reg_t) bytes[3]) << 24) |
+        (((reg_t) bytes[4]) << 32) |
+        (((reg_t) bytes[5]) << 40) |
+        (((reg_t) bytes[6]) << 48) |
+        (((reg_t) bytes[7]) << 56);
+  }
+  abort();
+}
 
-  tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
-  tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
-  tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
-  tlb_data[idx] = (long)(pte >> PTE_PPN_SHIFT << PGSHIFT) + (long)mem;
+void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
+{
+  reg_t paddr = translate(addr, LOAD);
+
+  if (auto host_addr = sim->addr_to_mem(paddr)) {
+    memcpy(bytes, host_addr, len);
+    if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
+      tracer.trace(paddr, len, LOAD);
+    else
+      refill_tlb(addr, paddr, host_addr, LOAD);
+  } else if (!sim->mmio_load(paddr, len, bytes)) {
+    throw trap_load_access_fault(addr);
+  }
 
-  return (void*)(((long)addr & (PGSIZE-1)) + tlb_data[idx]);
+  if (!matched_trigger) {
+    reg_t data = reg_from_bytes(len, bytes);
+    matched_trigger = trigger_exception(OPERATION_LOAD, addr, data);
+    if (matched_trigger)
+      throw *matched_trigger;
+  }
 }
 
-pte_t mmu_t::walk(reg_t addr)
+void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
 {
-  pte_t pte = 0;
+  reg_t paddr = translate(addr, STORE);
 
-  if(!vm_enabled)
-  {
-    if(addr < memsz)
-      pte = PTE_E | PTE_PERM | ((addr >> PGSHIFT) << PTE_PPN_SHIFT);
+  if (!matched_trigger) {
+    reg_t data = reg_from_bytes(len, bytes);
+    matched_trigger = trigger_exception(OPERATION_STORE, addr, data);
+    if (matched_trigger)
+      throw *matched_trigger;
   }
-  else
-  {
-    reg_t base = ptbr;
-    reg_t ptd;
-
-    int ptshift = (LEVELS-1)*PTIDXBITS;
-    for(reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS)
-    {
-      reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1);
-
-      reg_t pte_addr = base + idx*sizeof(pte_t);
-      if(pte_addr >= memsz)
-        break;
 
-      ptd = *(pte_t*)(mem+pte_addr);
-      if(ptd & PTE_E)
-      {
-        // if this PTE is from a larger PT, fake a leaf
-        // PTE so the TLB will work right
-        reg_t vpn = addr >> PGSHIFT;
-        ptd |= (vpn & ((1<<(ptshift))-1)) << PTE_PPN_SHIFT;
-
-        // fault if physical addr is invalid
-        reg_t ppn = ptd >> PTE_PPN_SHIFT;
-        if((ppn << PGSHIFT) + (addr & (PGSIZE-1)) < memsz)
-          pte = ptd;
-        break;
-      }
-      else if(!(ptd & PTE_T))
-        break;
+  if (auto host_addr = sim->addr_to_mem(paddr)) {
+    memcpy(host_addr, bytes, len);
+    if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
+      tracer.trace(paddr, len, STORE);
+    else
+      refill_tlb(addr, paddr, host_addr, STORE);
+  } else if (!sim->mmio_store(paddr, len, bytes)) {
+    throw trap_store_access_fault(addr);
+  }
+}
 
-      base = (ptd >> PTE_PPN_SHIFT) << PGSHIFT;
+tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_type type)
+{
+  reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
+  reg_t expected_tag = vaddr >> PGSHIFT;
+
+  if ((tlb_load_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag)
+    tlb_load_tag[idx] = -1;
+  if ((tlb_store_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag)
+    tlb_store_tag[idx] = -1;
+  if ((tlb_insn_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag)
+    tlb_insn_tag[idx] = -1;
+
+  if ((check_triggers_fetch && type == FETCH) ||
+      (check_triggers_load && type == LOAD) ||
+      (check_triggers_store && type == STORE))
+    expected_tag |= TLB_CHECK_TRIGGERS;
+
+  if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
+  else if (type == STORE) tlb_store_tag[idx] = expected_tag;
+  else tlb_load_tag[idx] = expected_tag;
+
+  tlb_entry_t entry = {host_addr - vaddr, paddr - vaddr};
+  tlb_data[idx] = entry;
+  return entry;
+}
+
+reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
+{
+  vm_info vm = decode_vm_info(proc->max_xlen, mode, proc->get_state()->satp);
+  if (vm.levels == 0)
+    return addr & ((reg_t(2) << (proc->xlen-1))-1); // zero-extend from xlen
+
+  bool s_mode = mode == PRV_S;
+  bool sum = get_field(proc->state.mstatus, MSTATUS_SUM);
+  bool mxr = get_field(proc->state.mstatus, MSTATUS_MXR);
+
+  // verify bits xlen-1:va_bits-1 are all equal
+  int va_bits = PGSHIFT + vm.levels * vm.idxbits;
+  reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
+  reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
+  if (masked_msbs != 0 && masked_msbs != mask)
+    vm.levels = 0;
+
+  reg_t base = vm.ptbase;
+  for (int i = vm.levels - 1; i >= 0; i--) {
+    int ptshift = i * vm.idxbits;
+    reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << vm.idxbits) - 1);
+
+    // check that physical address of PTE is legal
+    auto ppte = sim->addr_to_mem(base + idx * vm.ptesize);
+    if (!ppte)
+      goto fail_access;
+
+    reg_t pte = vm.ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
+    reg_t ppn = pte >> PTE_PPN_SHIFT;
+
+    if (PTE_TABLE(pte)) { // next level of page table
+      base = ppn << PGSHIFT;
+    } else if ((pte & PTE_U) ? s_mode && (type == FETCH || !sum) : !s_mode) {
+      break;
+    } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
+      break;
+    } else if (type == FETCH ? !(pte & PTE_X) :
+               type == LOAD ?  !(pte & PTE_R) && !(mxr && (pte & PTE_X)) :
+                               !((pte & PTE_R) && (pte & PTE_W))) {
+      break;
+    } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) {
+      break;
+    } else {
+      reg_t ad = PTE_A | ((type == STORE) * PTE_D);
+#ifdef RISCV_ENABLE_DIRTY
+      // set accessed and possibly dirty bits.
+      *(uint32_t*)ppte |= ad;
+#else
+      // take exception if access or possibly dirty bit is not set.
+      if ((pte & ad) != ad)
+        break;
+#endif
+      // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
+      reg_t vpn = addr >> PGSHIFT;
+      reg_t value = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
+      return value;
     }
   }
 
-  return pte;
+fail:
+  switch (type) {
+    case FETCH: throw trap_instruction_page_fault(addr);
+    case LOAD: throw trap_load_page_fault(addr);
+    case STORE: throw trap_store_page_fault(addr);
+    default: abort();
+  }
+
+fail_access:
+  switch (type) {
+    case FETCH: throw trap_instruction_access_fault(addr);
+    case LOAD: throw trap_load_access_fault(addr);
+    case STORE: throw trap_store_access_fault(addr);
+    default: abort();
+  }
+}
+
+void mmu_t::register_memtracer(memtracer_t* t)
+{
+  flush_tlb();
+  tracer.hook(t);
 }