X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=00eccc882d45713c999694f2c520c24cbe212846;hb=4f8b6a69484bd901f213d9a73ea29d26c8022dfd;hp=34735f95fce0dc838d95b9ec6018248815473943;hpb=5618582e2fdbece0c3125c430fc660faea479b62;p=riscv-isa-sim.git diff --git a/riscv/processor.cc b/riscv/processor.cc index 34735f9..00eccc8 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -5,7 +5,7 @@ #include "common.h" #include "config.h" #include "sim.h" -#include "htif.h" +#include "mmu.h" #include "disasm.h" #include #include @@ -19,18 +19,18 @@ #undef STATE #define STATE state -processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id) - : sim(sim), ext(NULL), disassembler(new disassembler_t), - id(id), run(false), debug(false) +processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id, + bool halt_on_reset) + : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), + halt_on_reset(halt_on_reset) { parse_isa_string(isa); + register_base_instructions(); - mmu = new mmu_t(sim->mem, sim->memsz); - mmu->set_processor(this); - - reset(true); + mmu = new mmu_t(sim, this); + disassembler = new disassembler_t(max_xlen); - register_base_instructions(); + reset(); } processor_t::~processor_t() @@ -67,7 +67,7 @@ void processor_t::parse_isa_string(const char* str) isa = reg_t(2) << 62; if (strncmp(p, "rv32", 4) == 0) - max_xlen = 32, isa = 0, p += 4; + max_xlen = 32, isa = reg_t(1) << 30, p += 4; else if (strncmp(p, "rv64", 4) == 0) p += 4; else if (strncmp(p, "rv", 2) == 0) @@ -84,6 +84,7 @@ void processor_t::parse_isa_string(const char* str) isa_string = "rv" + std::to_string(max_xlen) + p; isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode + isa |= 1L << ('u' - 'a'); // advertise support for user mode while (*p) { isa |= 1L << (*p - 'a'); @@ -105,14 +106,11 @@ void processor_t::parse_isa_string(const char* str) if (supports_extension('D') && !supports_extension('F')) bad_isa_string(str); - // if we have IMAFD, advertise G, too - if (supports_extension('I') && supports_extension('M') && - supports_extension('A') && supports_extension('D')) - isa |= 1L << ('g' - 'a'); - // advertise support for supervisor and user modes isa |= 1L << ('s' - 'a'); isa |= 1L << ('u' - 'a'); + + max_isa = isa; } void state_t::reset() @@ -121,6 +119,9 @@ void state_t::reset() prv = PRV_M; pc = DEFAULT_RSTVEC; load_reservation = -1; + tselect = 0; + for (unsigned int i = 0; i < num_triggers; i++) + mcontrol[i].type = 2; } void processor_t::set_debug(bool value) @@ -141,24 +142,18 @@ void processor_t::set_histogram(bool value) #endif } -void processor_t::reset(bool value) +void processor_t::reset() { - if (run == !value) - return; - run = !value; - state.reset(); + state.dcsr.halt = halt_on_reset; + halt_on_reset = false; set_csr(CSR_MSTATUS, state.mstatus); if (ext) ext->reset(); // reset the extension } -void processor_t::raise_interrupt(reg_t which) -{ - throw trap_t(((reg_t)1 << (max_xlen-1)) | which); -} - +// Count number of contiguous 0 bits starting from the LSB. static int ctz(reg_t val) { int res = 0; @@ -168,51 +163,81 @@ static int ctz(reg_t val) return res; } -void processor_t::take_interrupt() +void processor_t::take_interrupt(reg_t pending_interrupts) { - check_timer(); - - reg_t interrupts = state.mip & state.mie; - - reg_t m_interrupts = interrupts & ~state.mideleg; reg_t mie = get_field(state.mstatus, MSTATUS_MIE); - if ((state.prv < PRV_M || (state.prv == PRV_M && mie)) && m_interrupts) - raise_interrupt(ctz(m_interrupts)); + reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie); + reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled; - reg_t s_interrupts = interrupts & state.mideleg; reg_t sie = get_field(state.mstatus, MSTATUS_SIE); - if ((state.prv < PRV_S || (state.prv == PRV_S && sie)) && s_interrupts) - raise_interrupt(ctz(s_interrupts)); -} + reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie); + if (enabled_interrupts == 0) + enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled; -void processor_t::check_timer() -{ - if (sim->rtc >= state.mtimecmp) - state.mip |= MIP_MTIP; + if (enabled_interrupts) + throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts)); } -static bool validate_priv(reg_t priv) +static int xlen_to_uxl(int xlen) { - return priv == PRV_U || priv == PRV_S || priv == PRV_M; + if (xlen == 32) + return 1; + if (xlen == 64) + return 2; + abort(); } void processor_t::set_privilege(reg_t prv) { - assert(validate_priv(prv)); + assert(prv <= PRV_M); + if (prv == PRV_H) + prv = PRV_U; mmu->flush_tlb(); state.prv = prv; } +void processor_t::enter_debug_mode(uint8_t cause) +{ + state.dcsr.cause = cause; + state.dcsr.prv = state.prv; + set_privilege(PRV_M); + state.dpc = state.pc; + state.pc = DEBUG_ROM_ENTRY; +} + void processor_t::take_trap(trap_t& t, reg_t epc) { - if (debug) + if (debug) { fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n", id, t.name(), epc); + if (t.has_badaddr()) + fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id, + t.get_badaddr()); + } + + if (state.dcsr.cause) { + if (t.cause() == CAUSE_BREAKPOINT) { + state.pc = DEBUG_ROM_ENTRY; + } else { + state.pc = DEBUG_ROM_TVEC; + } + return; + } + + if (t.cause() == CAUSE_BREAKPOINT && ( + (state.prv == PRV_M && state.dcsr.ebreakm) || + (state.prv == PRV_H && state.dcsr.ebreakh) || + (state.prv == PRV_S && state.dcsr.ebreaks) || + (state.prv == PRV_U && state.dcsr.ebreaku))) { + enter_debug_mode(DCSR_CAUSE_SWBP); + return; + } // by default, trap to M-mode, unless delegated to S-mode reg_t bit = t.cause(); reg_t deleg = state.medeleg; - if (bit & ((reg_t)1 << (max_xlen-1))) + bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0; + if (interrupt) deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1)); if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) { // handle the trap in S-mode @@ -223,20 +248,21 @@ void processor_t::take_trap(trap_t& t, reg_t epc) state.sbadaddr = t.get_badaddr(); reg_t s = state.mstatus; - s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv)); + s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s = set_field(s, MSTATUS_SPP, state.prv); s = set_field(s, MSTATUS_SIE, 0); set_csr(CSR_MSTATUS, s); set_privilege(PRV_S); } else { - state.pc = DEFAULT_MTVEC; - state.mcause = t.cause(); + reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0; + state.pc = (state.mtvec & ~(reg_t)1) + vector; state.mepc = epc; + state.mcause = t.cause(); if (t.has_badaddr()) state.mbadaddr = t.get_badaddr(); reg_t s = state.mstatus; - s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv)); + s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s = set_field(s, MSTATUS_MPP, state.prv); s = set_field(s, MSTATUS_MIE, 0); set_csr(CSR_MSTATUS, s); @@ -248,25 +274,36 @@ void processor_t::take_trap(trap_t& t, reg_t epc) void processor_t::disasm(insn_t insn) { + static uint64_t last_pc = 1, last_bits; + static uint64_t executions = 1; + uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1); - fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", - id, state.pc, bits, disassembler->disassemble(insn).c_str()); + if (last_pc != state.pc || last_bits != bits) { + if (executions != 1) { + fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions); + } + + fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", + id, state.pc, bits, disassembler->disassemble(insn).c_str()); + last_pc = state.pc; + last_bits = bits; + executions = 1; + } else { + executions++; + } } -static bool validate_vm(int max_xlen, reg_t vm) +int processor_t::paddr_bits() { - if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48)) - return true; - if (max_xlen == 32 && vm == VM_SV32) - return true; - return vm == VM_MBARE; + assert(xlen == max_xlen); + return max_xlen == 64 ? 50 : 34; } void processor_t::set_csr(int which, reg_t val) { val = zext_xlen(val); - reg_t all_ints = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | (1UL << IRQ_HOST); - reg_t s_ints = MIP_SSIP | MIP_STIP; + reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP); + reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; switch (which) { case CSR_FFLAGS: @@ -284,17 +321,14 @@ void processor_t::set_csr(int which, reg_t val) break; case CSR_MSTATUS: { if ((val ^ state.mstatus) & - (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM)) + (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR)) mmu->flush_tlb(); reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE - | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM - | (ext ? MSTATUS_XS : 0); - - if (validate_vm(max_xlen, get_field(val, MSTATUS_VM))) - mask |= MSTATUS_VM; - if (validate_priv(get_field(val, MSTATUS_MPP))) - mask |= MSTATUS_MPP; + | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM + | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM + | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL | + (ext ? MSTATUS_XS : 0); state.mstatus = (state.mstatus & ~mask) | (val & mask); @@ -305,24 +339,22 @@ void processor_t::set_csr(int which, reg_t val) else state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty); - // spike supports the notion of xlen < max_xlen, but current priv spec - // doesn't provide a mechanism to run RV32 software on an RV64 machine + state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen)); + state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen)); + // U-XLEN == S-XLEN == M-XLEN xlen = max_xlen; break; } case CSR_MIP: { - reg_t mask = all_ints &~ MIP_MTIP; + reg_t mask = MIP_SSIP | MIP_STIP; state.mip = (state.mip & ~mask) | (val & mask); break; } - case CSR_MIPI: - state.mip = set_field(state.mip, MIP_MSIP, val & 1); - break; case CSR_MIE: state.mie = (state.mie & ~all_ints) | (val & all_ints); break; case CSR_MIDELEG: - state.mideleg = (state.mideleg & ~s_ints) | (val & s_ints); + state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints); break; case CSR_MEDELEG: { reg_t mask = 0; @@ -332,49 +364,150 @@ void processor_t::set_csr(int which, reg_t val) state.medeleg = (state.medeleg & ~mask) | (val & mask); break; } + case CSR_MINSTRET: + case CSR_MCYCLE: + if (xlen == 32) + state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU); + else + state.minstret = val; + break; + case CSR_MINSTRETH: + case CSR_MCYCLEH: + state.minstret = (val << 32) | (state.minstret << 32 >> 32); + break; + case CSR_SCOUNTEREN: + state.scounteren = val; + break; + case CSR_MCOUNTEREN: + state.mcounteren = val; + break; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS - | SSTATUS_XS | SSTATUS_PUM; - set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask)); - break; + | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR; + return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask)); } case CSR_SIP: { - reg_t mask = s_ints &~ MIP_STIP; - state.mip = (state.mip & ~mask) | (val & mask); - break; + reg_t mask = MIP_SSIP & state.mideleg; + return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask)); } - case CSR_SIE: { - reg_t mask = s_ints; - state.mie = (state.mie & ~mask) | (val & mask); + case CSR_SIE: + return set_csr(CSR_MIE, + (state.mie & ~state.mideleg) | (val & state.mideleg)); + case CSR_SPTBR: { + mmu->flush_tlb(); + if (max_xlen == 32) + state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE); + if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF || + get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 || + get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48)) + state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE); break; } case CSR_SEPC: state.sepc = val; break; case CSR_STVEC: state.stvec = val >> 2 << 2; break; - case CSR_SPTBR: state.sptbr = val; break; case CSR_SSCRATCH: state.sscratch = val; break; case CSR_SCAUSE: state.scause = val; break; case CSR_SBADADDR: state.sbadaddr = val; break; case CSR_MEPC: state.mepc = val; break; + case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break; case CSR_MSCRATCH: state.mscratch = val; break; case CSR_MCAUSE: state.mcause = val; break; case CSR_MBADADDR: state.mbadaddr = val; break; - case CSR_MTIMECMP: - state.mip &= ~MIP_MTIP; - state.mtimecmp = val; + case CSR_MISA: { + if (!(val & (1L << ('F' - 'A')))) + val &= ~(1L << ('D' - 'A')); + + // allow MAFDC bits in MISA to be modified + reg_t mask = 0; + mask |= 1L << ('M' - 'A'); + mask |= 1L << ('A' - 'A'); + mask |= 1L << ('F' - 'A'); + mask |= 1L << ('D' - 'A'); + mask |= 1L << ('C' - 'A'); + mask &= max_isa; + + isa = (val & mask) | (isa & ~mask); + break; + } + case CSR_TSELECT: + if (val < state.num_triggers) { + state.tselect = val; + } + break; + case CSR_TDATA1: + { + mcontrol_t *mc = &state.mcontrol[state.tselect]; + if (mc->dmode && !state.dcsr.cause) { + break; + } + mc->dmode = get_field(val, MCONTROL_DMODE(xlen)); + mc->select = get_field(val, MCONTROL_SELECT); + mc->timing = get_field(val, MCONTROL_TIMING); + mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION); + mc->chain = get_field(val, MCONTROL_CHAIN); + mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH); + mc->m = get_field(val, MCONTROL_M); + mc->h = get_field(val, MCONTROL_H); + mc->s = get_field(val, MCONTROL_S); + mc->u = get_field(val, MCONTROL_U); + mc->execute = get_field(val, MCONTROL_EXECUTE); + mc->store = get_field(val, MCONTROL_STORE); + mc->load = get_field(val, MCONTROL_LOAD); + // Assume we're here because of csrw. + if (mc->execute) + mc->timing = 0; + trigger_updated(); + } + break; + case CSR_TDATA2: + if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) { + break; + } + if (state.tselect < state.num_triggers) { + state.tdata2[state.tselect] = val; + } + break; + case CSR_DCSR: + state.dcsr.prv = get_field(val, DCSR_PRV); + state.dcsr.step = get_field(val, DCSR_STEP); + // TODO: ndreset and fullreset + state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM); + state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH); + state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS); + state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU); + state.dcsr.halt = get_field(val, DCSR_HALT); break; - case CSR_MTOHOST: - if (state.tohost == 0) - state.tohost = val; + case CSR_DPC: + state.dpc = val; break; - case CSR_MFROMHOST: - state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0); - state.fromhost = val; + case CSR_DSCRATCH: + state.dscratch = val; break; } } reg_t processor_t::get_csr(int which) { + uint32_t ctr_en = -1; + if (state.prv < PRV_M) + ctr_en &= state.mcounteren; + if (state.prv < PRV_S) + ctr_en &= state.scounteren; + bool ctr_ok = (ctr_en >> (which & 31)) & 1; + + if (ctr_ok) { + if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31) + return 0; + if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H) + return 0; + } + if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31) + return 0; + if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H) + return 0; + if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31) + return 0; + switch (which) { case CSR_FFLAGS: @@ -392,23 +525,32 @@ reg_t processor_t::get_csr(int which) if (!supports_extension('F')) break; return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT); - case CSR_MTIME: return sim->rtc; - case CSR_MCYCLE: return state.minstret; - case CSR_MINSTRET: return state.minstret; - case CSR_MTIMEH: if (xlen > 32) break; else return sim->rtc >> 32; - case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32; - case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32; + case CSR_INSTRET: + case CSR_CYCLE: + if (ctr_ok) + return state.minstret; + break; + case CSR_MINSTRET: + case CSR_MCYCLE: + return state.minstret; + case CSR_MINSTRETH: + case CSR_MCYCLEH: + if (xlen == 32) + return state.minstret >> 32; + break; + case CSR_SCOUNTEREN: return state.scounteren; + case CSR_MCOUNTEREN: return state.mcounteren; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS - | SSTATUS_XS | SSTATUS_PUM; + | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL; reg_t sstatus = state.mstatus & mask; if ((sstatus & SSTATUS_FS) == SSTATUS_FS || (sstatus & SSTATUS_XS) == SSTATUS_XS) sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD); return sstatus; } - case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP); - case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP); + case CSR_SIP: return state.mip & state.mideleg; + case CSR_SIE: return state.mie & state.mideleg; case CSR_SEPC: return state.sepc; case CSR_SBADADDR: return state.sbadaddr; case CSR_STVEC: return state.stvec; @@ -416,57 +558,85 @@ reg_t processor_t::get_csr(int which) if (max_xlen > xlen) return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1)); return state.scause; - case CSR_SPTBR: return state.sptbr; - case CSR_SASID: return 0; + case CSR_SPTBR: + if (get_field(state.mstatus, MSTATUS_TVM)) + require_privilege(PRV_M); + return state.sptbr; case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; - case CSR_MIPI: return 0; case CSR_MIE: return state.mie; case CSR_MEPC: return state.mepc; case CSR_MSCRATCH: return state.mscratch; case CSR_MCAUSE: return state.mcause; case CSR_MBADADDR: return state.mbadaddr; - case CSR_MTIMECMP: return state.mtimecmp; case CSR_MISA: return isa; case CSR_MARCHID: return 0; case CSR_MIMPID: return 0; case CSR_MVENDORID: return 0; case CSR_MHARTID: return id; - case CSR_MTVEC: return DEFAULT_MTVEC; + case CSR_MTVEC: return state.mtvec; case CSR_MEDELEG: return state.medeleg; case CSR_MIDELEG: return state.mideleg; - case CSR_MTOHOST: - sim->get_htif()->tick(); // not necessary, but faster - return state.tohost; - case CSR_MFROMHOST: - sim->get_htif()->tick(); // not necessary, but faster - return state.fromhost; - case CSR_MCFGADDR: return sim->memsz; - case CSR_UARCH0: - case CSR_UARCH1: - case CSR_UARCH2: - case CSR_UARCH3: - case CSR_UARCH4: - case CSR_UARCH5: - case CSR_UARCH6: - case CSR_UARCH7: - case CSR_UARCH8: - case CSR_UARCH9: - case CSR_UARCH10: - case CSR_UARCH11: - case CSR_UARCH12: - case CSR_UARCH13: - case CSR_UARCH14: - case CSR_UARCH15: - return 0; + case CSR_TSELECT: return state.tselect; + case CSR_TDATA1: + if (state.tselect < state.num_triggers) { + reg_t v = 0; + mcontrol_t *mc = &state.mcontrol[state.tselect]; + v = set_field(v, MCONTROL_TYPE(xlen), mc->type); + v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode); + v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax); + v = set_field(v, MCONTROL_SELECT, mc->select); + v = set_field(v, MCONTROL_TIMING, mc->timing); + v = set_field(v, MCONTROL_ACTION, mc->action); + v = set_field(v, MCONTROL_CHAIN, mc->chain); + v = set_field(v, MCONTROL_MATCH, mc->match); + v = set_field(v, MCONTROL_M, mc->m); + v = set_field(v, MCONTROL_H, mc->h); + v = set_field(v, MCONTROL_S, mc->s); + v = set_field(v, MCONTROL_U, mc->u); + v = set_field(v, MCONTROL_EXECUTE, mc->execute); + v = set_field(v, MCONTROL_STORE, mc->store); + v = set_field(v, MCONTROL_LOAD, mc->load); + return v; + } else { + return 0; + } + break; + case CSR_TDATA2: + if (state.tselect < state.num_triggers) { + return state.tdata2[state.tselect]; + } else { + return 0; + } + break; + case CSR_TDATA3: return 0; + case CSR_DCSR: + { + uint32_t v = 0; + v = set_field(v, DCSR_XDEBUGVER, 1); + v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm); + v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh); + v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks); + v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku); + v = set_field(v, DCSR_STOPCYCLE, 0); + v = set_field(v, DCSR_STOPTIME, 0); + v = set_field(v, DCSR_CAUSE, state.dcsr.cause); + v = set_field(v, DCSR_STEP, state.dcsr.step); + v = set_field(v, DCSR_PRV, state.dcsr.prv); + return v; + } + case CSR_DPC: + return state.dpc; + case CSR_DSCRATCH: + return state.dscratch; } - throw trap_illegal_instruction(); + throw trap_illegal_instruction(0); } reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc) { - throw trap_illegal_instruction(); + throw trap_illegal_instruction(0); } insn_func_t processor_t::decode_insn(insn_t insn) @@ -515,7 +685,7 @@ void processor_t::build_opcode_map() std::sort(instructions.begin(), instructions.end(), cmp()); for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++) - opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction}; + opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction}; } void processor_t::register_extension(extension_t* x) @@ -549,23 +719,51 @@ void processor_t::register_base_instructions() bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes) { - try { - auto res = get_csr(addr / (max_xlen / 8)); - memcpy(bytes, &res, len); - return true; - } catch (trap_illegal_instruction& t) { - return false; + switch (addr) + { + case 0: + if (len <= 4) { + memset(bytes, 0, len); + bytes[0] = get_field(state.mip, MIP_MSIP); + return true; + } + break; } + + return false; } bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes) { - try { - reg_t value = 0; - memcpy(&value, bytes, len); - set_csr(addr / (max_xlen / 8), value); - return true; - } catch (trap_illegal_instruction& t) { - return false; + switch (addr) + { + case 0: + if (len <= 4) { + state.mip = set_field(state.mip, MIP_MSIP, bytes[0]); + return true; + } + break; + } + + return false; +} + +void processor_t::trigger_updated() +{ + mmu->flush_tlb(); + mmu->check_triggers_fetch = false; + mmu->check_triggers_load = false; + mmu->check_triggers_store = false; + + for (unsigned i = 0; i < state.num_triggers; i++) { + if (state.mcontrol[i].execute) { + mmu->check_triggers_fetch = true; + } + if (state.mcontrol[i].load) { + mmu->check_triggers_load = true; + } + if (state.mcontrol[i].store) { + mmu->check_triggers_store = true; + } } }