X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=00eccc882d45713c999694f2c520c24cbe212846;hb=4f8b6a69484bd901f213d9a73ea29d26c8022dfd;hp=7d8c5df64e9cb6f78d3b57c810983d5c22aec2cd;hpb=c8149cb261631aadfe6d984cb9b40b88bfb31408;p=riscv-isa-sim.git diff --git a/riscv/processor.cc b/riscv/processor.cc index 7d8c5df..00eccc8 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -7,7 +7,6 @@ #include "sim.h" #include "mmu.h" #include "disasm.h" -#include "gdbserver.h" #include #include #include @@ -22,7 +21,8 @@ processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id, bool halt_on_reset) - : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset) + : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), + halt_on_reset(halt_on_reset) { parse_isa_string(isa); register_base_instructions(); @@ -109,6 +109,8 @@ void processor_t::parse_isa_string(const char* str) // advertise support for supervisor and user modes isa |= 1L << ('s' - 'a'); isa |= 1L << ('u' - 'a'); + + max_isa = isa; } void state_t::reset() @@ -116,14 +118,10 @@ void state_t::reset() memset(this, 0, sizeof(*this)); prv = PRV_M; pc = DEFAULT_RSTVEC; - mtvec = DEFAULT_MTVEC; load_reservation = -1; tselect = 0; - for (unsigned int i = 0; i < num_triggers; i++) { + for (unsigned int i = 0; i < num_triggers; i++) mcontrol[i].type = 2; - mcontrol[i].action = ACTION_NONE; - tdata1[i] = 0; - } } void processor_t::set_debug(bool value) @@ -155,11 +153,6 @@ void processor_t::reset() ext->reset(); // reset the extension } -void processor_t::raise_interrupt(reg_t which) -{ - throw trap_t(((reg_t)1 << (max_xlen-1)) | which); -} - // Count number of contiguous 0 bits starting from the LSB. static int ctz(reg_t val) { @@ -170,20 +163,28 @@ static int ctz(reg_t val) return res; } -void processor_t::take_interrupt() +void processor_t::take_interrupt(reg_t pending_interrupts) { - reg_t pending_interrupts = state.mip & state.mie; - reg_t mie = get_field(state.mstatus, MSTATUS_MIE); reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie); reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled; reg_t sie = get_field(state.mstatus, MSTATUS_SIE); reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie); - enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled; + if (enabled_interrupts == 0) + enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled; if (enabled_interrupts) - raise_interrupt(ctz(enabled_interrupts)); + throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts)); +} + +static int xlen_to_uxl(int xlen) +{ + if (xlen == 32) + return 1; + if (xlen == 64) + return 2; + abort(); } void processor_t::set_privilege(reg_t prv) @@ -201,7 +202,7 @@ void processor_t::enter_debug_mode(uint8_t cause) state.dcsr.prv = state.prv; set_privilege(PRV_M); state.dpc = state.pc; - state.pc = DEBUG_ROM_START; + state.pc = DEBUG_ROM_ENTRY; } void processor_t::take_trap(trap_t& t, reg_t epc) @@ -214,6 +215,15 @@ void processor_t::take_trap(trap_t& t, reg_t epc) t.get_badaddr()); } + if (state.dcsr.cause) { + if (t.cause() == CAUSE_BREAKPOINT) { + state.pc = DEBUG_ROM_ENTRY; + } else { + state.pc = DEBUG_ROM_TVEC; + } + return; + } + if (t.cause() == CAUSE_BREAKPOINT && ( (state.prv == PRV_M && state.dcsr.ebreakm) || (state.prv == PRV_H && state.dcsr.ebreakh) || @@ -223,15 +233,11 @@ void processor_t::take_trap(trap_t& t, reg_t epc) return; } - if (state.dcsr.cause) { - state.pc = DEBUG_ROM_EXCEPTION; - return; - } - // by default, trap to M-mode, unless delegated to S-mode reg_t bit = t.cause(); reg_t deleg = state.medeleg; - if (bit & ((reg_t)1 << (max_xlen-1))) + bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0; + if (interrupt) deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1)); if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) { // handle the trap in S-mode @@ -242,20 +248,21 @@ void processor_t::take_trap(trap_t& t, reg_t epc) state.sbadaddr = t.get_badaddr(); reg_t s = state.mstatus; - s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv)); + s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s = set_field(s, MSTATUS_SPP, state.prv); s = set_field(s, MSTATUS_SIE, 0); set_csr(CSR_MSTATUS, s); set_privilege(PRV_S); } else { - state.pc = state.mtvec; + reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0; + state.pc = (state.mtvec & ~(reg_t)1) + vector; state.mepc = epc; state.mcause = t.cause(); if (t.has_badaddr()) state.mbadaddr = t.get_badaddr(); reg_t s = state.mstatus; - s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv)); + s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s = set_field(s, MSTATUS_MPP, state.prv); s = set_field(s, MSTATUS_MIE, 0); set_csr(CSR_MSTATUS, s); @@ -267,18 +274,23 @@ void processor_t::take_trap(trap_t& t, reg_t epc) void processor_t::disasm(insn_t insn) { + static uint64_t last_pc = 1, last_bits; + static uint64_t executions = 1; + uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1); - fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", - id, state.pc, bits, disassembler->disassemble(insn).c_str()); -} + if (last_pc != state.pc || last_bits != bits) { + if (executions != 1) { + fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions); + } -static bool validate_vm(int max_xlen, reg_t vm) -{ - if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48)) - return true; - if (max_xlen == 32 && vm == VM_SV32) - return true; - return vm == VM_MBARE; + fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", + id, state.pc, bits, disassembler->disassemble(insn).c_str()); + last_pc = state.pc; + last_bits = bits; + executions = 1; + } else { + executions++; + } } int processor_t::paddr_bits() @@ -309,15 +321,14 @@ void processor_t::set_csr(int which, reg_t val) break; case CSR_MSTATUS: { if ((val ^ state.mstatus) & - (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR)) + (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR)) mmu->flush_tlb(); reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE - | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM - | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0); - - if (validate_vm(max_xlen, get_field(val, MSTATUS_VM))) - mask |= MSTATUS_VM; + | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM + | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM + | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL | + (ext ? MSTATUS_XS : 0); state.mstatus = (state.mstatus & ~mask) | (val & mask); @@ -328,8 +339,9 @@ void processor_t::set_csr(int which, reg_t val) else state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty); - // spike supports the notion of xlen < max_xlen, but current priv spec - // doesn't provide a mechanism to run RV32 software on an RV64 machine + state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen)); + state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen)); + // U-XLEN == S-XLEN == M-XLEN xlen = max_xlen; break; } @@ -352,26 +364,43 @@ void processor_t::set_csr(int which, reg_t val) state.medeleg = (state.medeleg & ~mask) | (val & mask); break; } - case CSR_MUCOUNTEREN: - state.mucounteren = val & 7; + case CSR_MINSTRET: + case CSR_MCYCLE: + if (xlen == 32) + state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU); + else + state.minstret = val; + break; + case CSR_MINSTRETH: + case CSR_MCYCLEH: + state.minstret = (val << 32) | (state.minstret << 32 >> 32); + break; + case CSR_SCOUNTEREN: + state.scounteren = val; break; - case CSR_MSCOUNTEREN: - state.mscounteren = val & 7; + case CSR_MCOUNTEREN: + state.mcounteren = val; break; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS - | SSTATUS_XS | SSTATUS_PUM; + | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR; return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask)); } - case CSR_SIP: - return set_csr(CSR_MIP, - (state.mip & ~state.mideleg) | (val & state.mideleg)); + case CSR_SIP: { + reg_t mask = MIP_SSIP & state.mideleg; + return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask)); + } case CSR_SIE: return set_csr(CSR_MIE, (state.mie & ~state.mideleg) | (val & state.mideleg)); case CSR_SPTBR: { - // upper bits of sptbr are the ASID; we only support ASID = 0 - state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1); + mmu->flush_tlb(); + if (max_xlen == 32) + state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE); + if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF || + get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 || + get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48)) + state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE); break; } case CSR_SEPC: state.sepc = val; break; @@ -380,15 +409,40 @@ void processor_t::set_csr(int which, reg_t val) case CSR_SCAUSE: state.scause = val; break; case CSR_SBADADDR: state.sbadaddr = val; break; case CSR_MEPC: state.mepc = val; break; - case CSR_MTVEC: state.mtvec = val >> 2 << 2; break; + case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break; case CSR_MSCRATCH: state.mscratch = val; break; case CSR_MCAUSE: state.mcause = val; break; case CSR_MBADADDR: state.mbadaddr = val; break; - case CSR_TSELECT: state.tselect = val; break; - case CSR_TDATA0: - if (state.tselect < state.num_triggers) { + case CSR_MISA: { + if (!(val & (1L << ('F' - 'A')))) + val &= ~(1L << ('D' - 'A')); + + // allow MAFDC bits in MISA to be modified + reg_t mask = 0; + mask |= 1L << ('M' - 'A'); + mask |= 1L << ('A' - 'A'); + mask |= 1L << ('F' - 'A'); + mask |= 1L << ('D' - 'A'); + mask |= 1L << ('C' - 'A'); + mask &= max_isa; + + isa = (val & mask) | (isa & ~mask); + break; + } + case CSR_TSELECT: + if (val < state.num_triggers) { + state.tselect = val; + } + break; + case CSR_TDATA1: + { mcontrol_t *mc = &state.mcontrol[state.tselect]; + if (mc->dmode && !state.dcsr.cause) { + break; + } + mc->dmode = get_field(val, MCONTROL_DMODE(xlen)); mc->select = get_field(val, MCONTROL_SELECT); + mc->timing = get_field(val, MCONTROL_TIMING); mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION); mc->chain = get_field(val, MCONTROL_CHAIN); mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH); @@ -400,12 +454,17 @@ void processor_t::set_csr(int which, reg_t val) mc->store = get_field(val, MCONTROL_STORE); mc->load = get_field(val, MCONTROL_LOAD); // Assume we're here because of csrw. + if (mc->execute) + mc->timing = 0; trigger_updated(); } break; - case CSR_TDATA1: + case CSR_TDATA2: + if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) { + break; + } if (state.tselect < state.num_triggers) { - state.tdata1[state.tselect] = val; + state.tdata2[state.tselect] = val; } break; case CSR_DCSR: @@ -429,6 +488,26 @@ void processor_t::set_csr(int which, reg_t val) reg_t processor_t::get_csr(int which) { + uint32_t ctr_en = -1; + if (state.prv < PRV_M) + ctr_en &= state.mcounteren; + if (state.prv < PRV_S) + ctr_en &= state.scounteren; + bool ctr_ok = (ctr_en >> (which & 31)) & 1; + + if (ctr_ok) { + if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31) + return 0; + if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H) + return 0; + } + if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31) + return 0; + if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H) + return 0; + if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31) + return 0; + switch (which) { case CSR_FFLAGS: @@ -446,39 +525,24 @@ reg_t processor_t::get_csr(int which) if (!supports_extension('F')) break; return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT); - case CSR_TIME: case CSR_INSTRET: case CSR_CYCLE: - if ((state.mucounteren >> (which & (xlen-1))) & 1) - return get_csr(which + (CSR_MCYCLE - CSR_CYCLE)); + if (ctr_ok) + return state.minstret; break; - case CSR_STIME: - case CSR_SINSTRET: - case CSR_SCYCLE: - if ((state.mscounteren >> (which & (xlen-1))) & 1) - return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE)); + case CSR_MINSTRET: + case CSR_MCYCLE: + return state.minstret; + case CSR_MINSTRETH: + case CSR_MCYCLEH: + if (xlen == 32) + return state.minstret >> 32; break; - case CSR_MUCOUNTEREN: return state.mucounteren; - case CSR_MSCOUNTEREN: return state.mscounteren; - case CSR_MUCYCLE_DELTA: return 0; - case CSR_MUTIME_DELTA: return 0; - case CSR_MUINSTRET_DELTA: return 0; - case CSR_MSCYCLE_DELTA: return 0; - case CSR_MSTIME_DELTA: return 0; - case CSR_MSINSTRET_DELTA: return 0; - case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0; - case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0; - case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0; - case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0; - case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0; - case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0; - case CSR_MCYCLE: return state.minstret; - case CSR_MINSTRET: return state.minstret; - case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32; - case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32; + case CSR_SCOUNTEREN: return state.scounteren; + case CSR_MCOUNTEREN: return state.mcounteren; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS - | SSTATUS_XS | SSTATUS_PUM; + | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL; reg_t sstatus = state.mstatus & mask; if ((sstatus & SSTATUS_FS) == SSTATUS_FS || (sstatus & SSTATUS_XS) == SSTATUS_XS) @@ -494,7 +558,10 @@ reg_t processor_t::get_csr(int which) if (max_xlen > xlen) return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1)); return state.scause; - case CSR_SPTBR: return state.sptbr; + case CSR_SPTBR: + if (get_field(state.mstatus, MSTATUS_TVM)) + require_privilege(PRV_M); + return state.sptbr; case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; @@ -512,13 +579,15 @@ reg_t processor_t::get_csr(int which) case CSR_MEDELEG: return state.medeleg; case CSR_MIDELEG: return state.mideleg; case CSR_TSELECT: return state.tselect; - case CSR_TDATA0: + case CSR_TDATA1: if (state.tselect < state.num_triggers) { reg_t v = 0; mcontrol_t *mc = &state.mcontrol[state.tselect]; - v = set_field(v, 0xfL << (xlen-4), mc->type); - v = set_field(v, 0x3fL << (xlen-10), mc->maskmax); + v = set_field(v, MCONTROL_TYPE(xlen), mc->type); + v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode); + v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax); v = set_field(v, MCONTROL_SELECT, mc->select); + v = set_field(v, MCONTROL_TIMING, mc->timing); v = set_field(v, MCONTROL_ACTION, mc->action); v = set_field(v, MCONTROL_CHAIN, mc->chain); v = set_field(v, MCONTROL_MATCH, mc->match); @@ -534,30 +603,27 @@ reg_t processor_t::get_csr(int which) return 0; } break; - case CSR_TDATA1: + case CSR_TDATA2: if (state.tselect < state.num_triggers) { - return state.tdata1[state.tselect]; + return state.tdata2[state.tselect]; } else { return 0; } break; + case CSR_TDATA3: return 0; case CSR_DCSR: { uint32_t v = 0; v = set_field(v, DCSR_XDEBUGVER, 1); - v = set_field(v, DCSR_NDRESET, 0); - v = set_field(v, DCSR_FULLRESET, 0); - v = set_field(v, DCSR_PRV, state.dcsr.prv); - v = set_field(v, DCSR_STEP, state.dcsr.step); - v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id)); - v = set_field(v, DCSR_STOPCYCLE, 0); - v = set_field(v, DCSR_STOPTIME, 0); v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm); v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh); v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks); v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku); - v = set_field(v, DCSR_HALT, state.dcsr.halt); + v = set_field(v, DCSR_STOPCYCLE, 0); + v = set_field(v, DCSR_STOPTIME, 0); v = set_field(v, DCSR_CAUSE, state.dcsr.cause); + v = set_field(v, DCSR_STEP, state.dcsr.step); + v = set_field(v, DCSR_PRV, state.dcsr.prv); return v; } case CSR_DPC: @@ -565,12 +631,12 @@ reg_t processor_t::get_csr(int which) case CSR_DSCRATCH: return state.dscratch; } - throw trap_illegal_instruction(); + throw trap_illegal_instruction(0); } reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc) { - throw trap_illegal_instruction(); + throw trap_illegal_instruction(0); } insn_func_t processor_t::decode_insn(insn_t insn) @@ -653,6 +719,17 @@ void processor_t::register_base_instructions() bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes) { + switch (addr) + { + case 0: + if (len <= 4) { + memset(bytes, 0, len); + bytes[0] = get_field(state.mip, MIP_MSIP); + return true; + } + break; + } + return false; } @@ -661,14 +738,14 @@ bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes) switch (addr) { case 0: - state.mip &= ~MIP_MSIP; - if (bytes[0] & 1) - state.mip |= MIP_MSIP; - return true; - - default: - return false; + if (len <= 4) { + state.mip = set_field(state.mip, MIP_MSIP, bytes[0]); + return true; + } + break; } + + return false; } void processor_t::trigger_updated() @@ -679,8 +756,6 @@ void processor_t::trigger_updated() mmu->check_triggers_store = false; for (unsigned i = 0; i < state.num_triggers; i++) { - if (state.mcontrol[i].action == ACTION_NONE) - continue; if (state.mcontrol[i].execute) { mmu->check_triggers_fetch = true; }