X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=0a344465df6b39ddf981e22b8c28f3ea4f67eeb2;hb=bf8c76bdbc924e52007d47168ef3f54d213fce8b;hp=78cb3f535d018b18fbe64260fbddc7f6069a8bd7;hpb=7cbbc8fd6a57988e151b33a311f12f0fdeffdab4;p=riscv-isa-sim.git

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 78cb3f5..0a34446 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -127,14 +127,16 @@ static void commit_log(state_t* state, reg_t pc, insn_t insn)
 {
 #ifdef RISCV_ENABLE_COMMITLOG
   if (state->sr & SR_EI) {
+    uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
     if (state->log_reg_write.addr) {
-      uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
-      fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIx64 " 0x%016" PRIx64 "\n",
-              pc, insn.bits() & mask,
+      fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
+              pc,
+              insn.bits() & mask,
               state->log_reg_write.addr & 1 ? 'f' : 'x',
-              state->log_reg_write.addr >> 1, state->log_reg_write.data);
+              state->log_reg_write.addr >> 1,
+              state->log_reg_write.data);
     } else {
-      fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits());
+      fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits() & mask);
     }
   }
   state->log_reg_write.addr = 0;