X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=548c649cd2fafd76fe92bb8929544cffac7d8433;hb=1da69b975beeda193d5fa47950be5883ca20ad13;hp=5a57c285c9bcada230568c2bc76991987c8a9fd3;hpb=90bafe660b323250338fd564bb9ab4316576d59b;p=riscv-isa-sim.git diff --git a/riscv/processor.cc b/riscv/processor.cc index 5a57c28..548c649 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -155,7 +155,8 @@ void processor_t::reset() if (ext) ext->reset(); // reset the extension - sim->proc_reset(id); + if (sim) + sim->proc_reset(id); } // Count number of contiguous 0 bits starting from the LSB. @@ -449,6 +450,10 @@ void processor_t::set_csr(int which, reg_t val) case CSR_MCAUSE: state.mcause = val; break; case CSR_MTVAL: state.mtval = val; break; case CSR_MISA: { + // the write is ignored if increasing IALIGN would misalign the PC + if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2)) + break; + if (!(val & (1L << ('F' - 'A')))) val &= ~(1L << ('D' - 'A')); @@ -591,7 +596,7 @@ reg_t processor_t::get_csr(int which) } case CSR_SIP: return state.mip & state.mideleg; case CSR_SIE: return state.mie & state.mideleg; - case CSR_SEPC: return state.sepc; + case CSR_SEPC: return state.sepc & pc_alignment_mask(); case CSR_STVAL: return state.stval; case CSR_STVEC: return state.stvec; case CSR_SCAUSE: @@ -606,7 +611,7 @@ reg_t processor_t::get_csr(int which) case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; case CSR_MIE: return state.mie; - case CSR_MEPC: return state.mepc; + case CSR_MEPC: return state.mepc & pc_alignment_mask(); case CSR_MSCRATCH: return state.mscratch; case CSR_MCAUSE: return state.mcause; case CSR_MTVAL: return state.mtval; @@ -667,7 +672,7 @@ reg_t processor_t::get_csr(int which) return v; } case CSR_DPC: - return state.dpc; + return state.dpc & pc_alignment_mask(); case CSR_DSCRATCH: return state.dscratch; }