X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=7a5df901b315c7a5b1642c45415520cdcb659ef3;hb=0020b3b924417412200b4ce7eb423b4213443b02;hp=2500c2bff182beb6c646cfc8aaa46bd856f69d44;hpb=bdd229b9ea9a78f2fe5d4af1d0a49cf50484aa86;p=riscv-isa-sim.git

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 2500c2b..7a5df90 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -115,9 +115,10 @@ void processor_t::parse_isa_string(const char* str)
   max_isa = state.misa;
 }
 
-void state_t::reset()
+void state_t::reset(reg_t max_isa)
 {
   memset(this, 0, sizeof(*this));
+  misa = max_isa;
   prv = PRV_M;
   pc = DEFAULT_RSTVEC;
   load_reservation = -1;
@@ -146,13 +147,16 @@ void processor_t::set_histogram(bool value)
 
 void processor_t::reset()
 {
-  state.reset();
+  state.reset(max_isa);
   state.dcsr.halt = halt_on_reset;
   halt_on_reset = false;
   set_csr(CSR_MSTATUS, state.mstatus);
 
   if (ext)
     ext->reset(); // reset the extension
+
+  if (sim)
+    sim->proc_reset(id);
 }
 
 // Count number of contiguous 0 bits starting from the LSB.