X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=7a5df901b315c7a5b1642c45415520cdcb659ef3;hb=0020b3b924417412200b4ce7eb423b4213443b02;hp=d6da193eba5baef80b0a56402507d8cc51243598;hpb=12b772563a33b6c6c3da0343fbfc747b1eeea6b6;p=riscv-isa-sim.git diff --git a/riscv/processor.cc b/riscv/processor.cc index d6da193..7a5df90 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -19,10 +19,10 @@ #undef STATE #define STATE state -processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id, +processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id, bool halt_on_reset) : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), - halt_on_reset(halt_on_reset) + halt_on_reset(halt_on_reset), last_pc(1), executions(1) { parse_isa_string(isa); register_base_instructions(); @@ -61,20 +61,20 @@ void processor_t::parse_isa_string(const char* str) lowercase += std::tolower(*r); const char* p = lowercase.c_str(); - const char* all_subsets = "imafdc"; + const char* all_subsets = "imafdqc"; max_xlen = 64; - isa = reg_t(2) << 62; + state.misa = reg_t(2) << 62; if (strncmp(p, "rv32", 4) == 0) - max_xlen = 32, isa = reg_t(1) << 30, p += 4; + max_xlen = 32, state.misa = reg_t(1) << 30, p += 4; else if (strncmp(p, "rv64", 4) == 0) p += 4; else if (strncmp(p, "rv", 2) == 0) p += 2; if (!*p) { - p = all_subsets; + p = "imafdc"; } else if (*p == 'g') { // treat "G" as "IMAFD" tmp = std::string("imafd") + (p+1); p = &tmp[0]; @@ -83,11 +83,11 @@ void processor_t::parse_isa_string(const char* str) } isa_string = "rv" + std::to_string(max_xlen) + p; - isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode - isa |= 1L << ('u' - 'a'); // advertise support for user mode + state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode + state.misa |= 1L << ('u' - 'a'); // advertise support for user mode while (*p) { - isa |= 1L << (*p - 'a'); + state.misa |= 1L << (*p - 'a'); if (auto next = strchr(all_subsets, *p)) { all_subsets = next + 1; @@ -106,16 +106,19 @@ void processor_t::parse_isa_string(const char* str) if (supports_extension('D') && !supports_extension('F')) bad_isa_string(str); - // advertise support for supervisor and user modes - isa |= 1L << ('s' - 'a'); - isa |= 1L << ('u' - 'a'); + if (supports_extension('Q') && !supports_extension('D')) + bad_isa_string(str); + + if (supports_extension('Q') && max_xlen < 64) + bad_isa_string(str); - max_isa = isa; + max_isa = state.misa; } -void state_t::reset() +void state_t::reset(reg_t max_isa) { memset(this, 0, sizeof(*this)); + misa = max_isa; prv = PRV_M; pc = DEFAULT_RSTVEC; load_reservation = -1; @@ -144,13 +147,16 @@ void processor_t::set_histogram(bool value) void processor_t::reset() { - state.reset(); + state.reset(max_isa); state.dcsr.halt = halt_on_reset; halt_on_reset = false; set_csr(CSR_MSTATUS, state.mstatus); if (ext) ext->reset(); // reset the extension + + if (sim) + sim->proc_reset(id); } // Count number of contiguous 0 bits starting from the LSB. @@ -171,30 +177,65 @@ void processor_t::take_interrupt(reg_t pending_interrupts) reg_t sie = get_field(state.mstatus, MSTATUS_SIE); reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie); + // M-ints have highest priority; consider S-ints only if no M-ints pending if (enabled_interrupts == 0) enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled; - if (enabled_interrupts) + if (state.dcsr.cause == 0 && enabled_interrupts) { + // nonstandard interrupts have highest priority + if (enabled_interrupts >> IRQ_M_EXT) + enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT; + // external interrupts have next-highest priority + else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP)) + enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP); + // software interrupts have next-highest priority + else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP)) + enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP); + // timer interrupts have next-highest priority + else if (enabled_interrupts & (MIP_MTIP | MIP_STIP)) + enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP); + else + abort(); + throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts)); + } } -void processor_t::set_privilege(reg_t prv) +static int xlen_to_uxl(int xlen) +{ + if (xlen == 32) + return 1; + if (xlen == 64) + return 2; + abort(); +} + +reg_t processor_t::legalize_privilege(reg_t prv) { assert(prv <= PRV_M); - if (prv == PRV_H) - prv = PRV_U; + + if (!supports_extension('U')) + return PRV_M; + + if (prv == PRV_H || !supports_extension('S')) + return PRV_U; + + return prv; +} + +void processor_t::set_privilege(reg_t prv) +{ mmu->flush_tlb(); - state.prv = prv; + state.prv = legalize_privilege(prv); } void processor_t::enter_debug_mode(uint8_t cause) { - fprintf(stderr, "Entering debug mode because of cause %d", cause); state.dcsr.cause = cause; state.dcsr.prv = state.prv; set_privilege(PRV_M); state.dpc = state.pc; - state.pc = debug_rom_entry(); + state.pc = DEBUG_ROM_ENTRY; } void processor_t::take_trap(trap_t& t, reg_t epc) @@ -202,25 +243,22 @@ void processor_t::take_trap(trap_t& t, reg_t epc) if (debug) { fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n", id, t.name(), epc); - if (t.has_badaddr()) - fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id, - t.get_badaddr()); + if (t.has_tval()) + fprintf(stderr, "core %3d: tval 0x%016" PRIx64 "\n", id, + t.get_tval()); } if (state.dcsr.cause) { if (t.cause() == CAUSE_BREAKPOINT) { - state.pc = debug_rom_entry(); - fprintf(stderr, "Breakpoint."); + state.pc = DEBUG_ROM_ENTRY; } else { - fprintf(stderr, "WE ARE IN DEBUG MODE, DEBUG_ROM_EXCEPTION\n"); - state.pc = DEBUG_ROM_EXCEPTION; + state.pc = DEBUG_ROM_TVEC; } return; } if (t.cause() == CAUSE_BREAKPOINT && ( (state.prv == PRV_M && state.dcsr.ebreakm) || - (state.prv == PRV_H && state.dcsr.ebreakh) || (state.prv == PRV_S && state.dcsr.ebreaks) || (state.prv == PRV_U && state.dcsr.ebreaku))) { enter_debug_mode(DCSR_CAUSE_SWBP); @@ -238,8 +276,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) state.pc = state.stvec; state.scause = t.cause(); state.sepc = epc; - if (t.has_badaddr()) - state.sbadaddr = t.get_badaddr(); + state.stval = t.get_tval(); reg_t s = state.mstatus; s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); @@ -252,8 +289,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) state.pc = (state.mtvec & ~(reg_t)1) + vector; state.mepc = epc; state.mcause = t.cause(); - if (t.has_badaddr()) - state.mbadaddr = t.get_badaddr(); + state.mtval = t.get_tval(); reg_t s = state.mstatus; s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); @@ -268,9 +304,6 @@ void processor_t::take_trap(trap_t& t, reg_t epc) void processor_t::disasm(insn_t insn) { - static uint64_t last_pc = 1, last_bits; - static uint64_t executions = 1; - uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1); if (last_pc != state.pc || last_bits != bits) { if (executions != 1) { @@ -319,9 +352,15 @@ void processor_t::set_csr(int which, reg_t val) mmu->flush_tlb(); reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE - | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM - | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM - | MSTATUS_TSR | (ext ? MSTATUS_XS : 0); + | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM + | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM + | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL | + (ext ? MSTATUS_XS : 0); + + reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP)); + state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp); + if (supports_extension('S')) + mask |= MSTATUS_SPP; state.mstatus = (state.mstatus & ~mask) | (val & mask); @@ -332,8 +371,10 @@ void processor_t::set_csr(int which, reg_t val) else state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty); - // spike supports the notion of xlen < max_xlen, but current priv spec - // doesn't provide a mechanism to run RV32 software on an RV64 machine + state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen)); + state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen)); + state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen)); + // U-XLEN == S-XLEN == M-XLEN xlen = max_xlen; break; } @@ -349,10 +390,13 @@ void processor_t::set_csr(int which, reg_t val) state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints); break; case CSR_MEDELEG: { - reg_t mask = 0; -#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value); -#include "encoding.h" -#undef DECLARE_CAUSE + reg_t mask = + (1 << CAUSE_MISALIGNED_FETCH) | + (1 << CAUSE_BREAKPOINT) | + (1 << CAUSE_USER_ECALL) | + (1 << CAUSE_FETCH_PAGE_FAULT) | + (1 << CAUSE_LOAD_PAGE_FAULT) | + (1 << CAUSE_STORE_PAGE_FAULT); state.medeleg = (state.medeleg & ~mask) | (val & mask); break; } @@ -385,26 +429,26 @@ void processor_t::set_csr(int which, reg_t val) case CSR_SIE: return set_csr(CSR_MIE, (state.mie & ~state.mideleg) | (val & state.mideleg)); - case CSR_SPTBR: { + case CSR_SATP: { mmu->flush_tlb(); if (max_xlen == 32) - state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE); - if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF || - get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 || - get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48)) - state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE); + state.satp = val & (SATP32_PPN | SATP32_MODE); + if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF || + get_field(val, SATP64_MODE) == SATP_MODE_SV39 || + get_field(val, SATP64_MODE) == SATP_MODE_SV48)) + state.satp = val & (SATP64_PPN | SATP64_MODE); break; } - case CSR_SEPC: state.sepc = val; break; + case CSR_SEPC: state.sepc = val & ~(reg_t)1; break; case CSR_STVEC: state.stvec = val >> 2 << 2; break; case CSR_SSCRATCH: state.sscratch = val; break; case CSR_SCAUSE: state.scause = val; break; - case CSR_SBADADDR: state.sbadaddr = val; break; - case CSR_MEPC: state.mepc = val; break; + case CSR_STVAL: state.stval = val; break; + case CSR_MEPC: state.mepc = val & ~(reg_t)1; break; case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break; case CSR_MSCRATCH: state.mscratch = val; break; case CSR_MCAUSE: state.mcause = val; break; - case CSR_MBADADDR: state.mbadaddr = val; break; + case CSR_MTVAL: state.mtval = val; break; case CSR_MISA: { if (!(val & (1L << ('F' - 'A')))) val &= ~(1L << ('D' - 'A')); @@ -418,7 +462,7 @@ void processor_t::set_csr(int which, reg_t val) mask |= 1L << ('C' - 'A'); mask &= max_isa; - isa = (val & mask) | (isa & ~mask); + state.misa = (val & mask) | (state.misa & ~mask); break; } case CSR_TSELECT: @@ -470,7 +514,7 @@ void processor_t::set_csr(int which, reg_t val) state.dcsr.halt = get_field(val, DCSR_HALT); break; case CSR_DPC: - state.dpc = val; + state.dpc = val & ~(reg_t)1; break; case CSR_DSCRATCH: state.dscratch = val; @@ -525,6 +569,11 @@ reg_t processor_t::get_csr(int which) case CSR_MINSTRET: case CSR_MCYCLE: return state.minstret; + case CSR_INSTRETH: + case CSR_CYCLEH: + if (ctr_ok && xlen == 32) + return state.minstret >> 32; + break; case CSR_MINSTRETH: case CSR_MCYCLEH: if (xlen == 32) @@ -534,7 +583,7 @@ reg_t processor_t::get_csr(int which) case CSR_MCOUNTEREN: return state.mcounteren; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS - | SSTATUS_XS | SSTATUS_SUM; + | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL; reg_t sstatus = state.mstatus & mask; if ((sstatus & SSTATUS_FS) == SSTATUS_FS || (sstatus & SSTATUS_XS) == SSTATUS_XS) @@ -544,16 +593,16 @@ reg_t processor_t::get_csr(int which) case CSR_SIP: return state.mip & state.mideleg; case CSR_SIE: return state.mie & state.mideleg; case CSR_SEPC: return state.sepc; - case CSR_SBADADDR: return state.sbadaddr; + case CSR_STVAL: return state.stval; case CSR_STVEC: return state.stvec; case CSR_SCAUSE: if (max_xlen > xlen) return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1)); return state.scause; - case CSR_SPTBR: + case CSR_SATP: if (get_field(state.mstatus, MSTATUS_TVM)) require_privilege(PRV_M); - return state.sptbr; + return state.satp; case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; @@ -561,8 +610,8 @@ reg_t processor_t::get_csr(int which) case CSR_MEPC: return state.mepc; case CSR_MSCRATCH: return state.mscratch; case CSR_MCAUSE: return state.mcause; - case CSR_MBADADDR: return state.mbadaddr; - case CSR_MISA: return isa; + case CSR_MTVAL: return state.mtval; + case CSR_MISA: return state.misa; case CSR_MARCHID: return 0; case CSR_MIMPID: return 0; case CSR_MVENDORID: return 0;