X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.cc;h=d6da193eba5baef80b0a56402507d8cc51243598;hb=12b772563a33b6c6c3da0343fbfc747b1eeea6b6;hp=ef529fc20c1d6d885b2fc7b22abad7060302a68c;hpb=6480784223919308b347162e8589f79cffc4615e;p=riscv-isa-sim.git

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ef529fc..d6da193 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -189,6 +189,7 @@ void processor_t::set_privilege(reg_t prv)
 
 void processor_t::enter_debug_mode(uint8_t cause)
 {
+  fprintf(stderr, "Entering debug mode because of cause %d", cause);
   state.dcsr.cause = cause;
   state.dcsr.prv = state.prv;
   set_privilege(PRV_M);
@@ -209,7 +210,9 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
   if (state.dcsr.cause) {
     if (t.cause() == CAUSE_BREAKPOINT) {
       state.pc = debug_rom_entry();
+      fprintf(stderr, "Breakpoint.");
     } else {
+      fprintf(stderr, "WE ARE IN DEBUG MODE, DEBUG_ROM_EXCEPTION\n");
       state.pc = DEBUG_ROM_EXCEPTION;
     }
     return;