X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.h;h=070fccf8af1d7515c1c46add649a2912b839da29;hb=4299874ad4b07ef457776513a64e5b2397a6a75e;hp=1b94b1f710e0c69d22e276318331a8e004d6e3cf;hpb=12714e371e9b8ce2efcf0e77347ed1b33c8de27b;p=riscv-isa-sim.git

diff --git a/riscv/processor.h b/riscv/processor.h
index 1b94b1f..070fccf 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -5,6 +5,7 @@
 #include "decode.h"
 #include "config.h"
 #include "devices.h"
+#include "trap.h"
 #include <string>
 #include <vector>
 #include <map>
@@ -184,6 +185,10 @@ public:
     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
     return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
   }
+  void check_pc_alignment(reg_t pc) {
+    if (unlikely(pc & 2) && !supports_extension('C'))
+      throw trap_instruction_address_misaligned(pc);
+  }
   reg_t legalize_privilege(reg_t);
   void set_privilege(reg_t);
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }