X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.h;h=31d5f6ca7dd442ef3005e04a4832823bdfbbcf77;hb=036c9086663024512dd0a8e5409b68187211c0bf;hp=2906bda182010cd228898dc9bbc6498ea0a7527d;hpb=b7fb80ccf514fe804cf112d7e8d11764ef93bca5;p=riscv-isa-sim.git

diff --git a/riscv/processor.h b/riscv/processor.h
index 2906bda..31d5f6c 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -106,9 +106,8 @@ public:
 
   void set_debug(bool value);
   void set_histogram(bool value);
-  void reset(bool value);
+  void reset();
   void step(size_t n); // run for n cycles
-  bool running() { return run; }
   void set_csr(int which, reg_t val);
   void raise_interrupt(reg_t which);
   reg_t get_csr(int which);
@@ -144,7 +143,6 @@ private:
   unsigned xlen;
   reg_t isa;
   std::string isa_string;
-  bool run; // !reset
   bool histogram_enabled;
   bool halt_on_reset;