X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.h;h=3e67215b46df9e29493b050c2d59e5cd586507cf;hb=1da69b975beeda193d5fa47950be5883ca20ad13;hp=ace86f963959145e3e8a7227f4fa2e91f0395e71;hpb=403438d6096f4a6bf0ff924f60940acf51c529a5;p=riscv-isa-sim.git

diff --git a/riscv/processor.h b/riscv/processor.h
index ace86f9..3e67215 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -188,8 +188,11 @@ public:
     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
     return ext >= 'A' && ext <= 'Z' && ((state.misa >> (ext - 'A')) & 1);
   }
+  reg_t pc_alignment_mask() {
+    return ~(reg_t)(supports_extension('C') ? 0 : 2);
+  }
   void check_pc_alignment(reg_t pc) {
-    if (unlikely(pc & 2) && !supports_extension('C'))
+    if (unlikely(pc & ~pc_alignment_mask()))
       throw trap_instruction_address_misaligned(pc);
   }
   reg_t legalize_privilege(reg_t);