X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.h;h=58c31cb3eb4c9309fc0adad599cc88f500b5c6c9;hb=616cc32c30ac0684edfd50ed44fc78ed1bc20884;hp=41268f9d2b40575e8f64954154e153700a9561b9;hpb=e2c0c3021ac2fa7cad5866e0f100c2dbf2372986;p=riscv-isa-sim.git

diff --git a/riscv/processor.h b/riscv/processor.h
index 41268f9..58c31cb 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -6,6 +6,7 @@
 #include "config.h"
 #include <cstring>
 #include <vector>
+#include <map>
 
 class processor_t;
 class mmu_t;
@@ -69,6 +70,7 @@ public:
   ~processor_t();
 
   void set_debug(bool value);
+  void set_histogram(bool value);
   void reset(bool value);
   void step(size_t n); // run for n cycles
   void deliver_ipi(); // register an interprocessor interrupt
@@ -81,6 +83,7 @@ public:
   state_t* get_state() { return &state; }
   extension_t* get_extension() { return ext; }
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
+  void update_histogram(size_t pc);
 
   void register_insn(insn_desc_t);
   void register_extension(extension_t*);
@@ -94,11 +97,13 @@ private:
   uint32_t id;
   bool run; // !reset
   bool debug;
+  bool histogram_enabled;
   bool rv64;
 
   std::vector<insn_desc_t> instructions;
   std::vector<insn_desc_t*> opcode_map;
   std::vector<insn_desc_t> opcode_store;
+  std::map<size_t,size_t> pc_histogram;
 
   void take_interrupt(); // take a trap if any interrupts are pending
   void take_trap(trap_t& t); // take an exception