X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.h;h=6e8d684ae573adb2220041c6ac4a835787475e83;hb=4f8b6a69484bd901f213d9a73ea29d26c8022dfd;hp=c294e5794853d7f69c4a60b1af139252205a65c5;hpb=6db070768733f415fc9bf54582708364ca0e294b;p=riscv-isa-sim.git

diff --git a/riscv/processor.h b/riscv/processor.h
index c294e57..6e8d684 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -8,6 +8,7 @@
 #include <string>
 #include <vector>
 #include <map>
+#include "debug_rom/debug_rom_defines.h"
 
 class processor_t;
 class mmu_t;
@@ -191,6 +192,8 @@ public:
   bool debug;
   // When true, take the slow simulation path.
   bool slow_path();
+  bool halted() { return state.dcsr.cause ? true : false; }
+  bool halt_request;
 
   // Return the index of a trigger that matched, or -1.
   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
@@ -306,7 +309,7 @@ private:
 
   friend class sim_t;
   friend class mmu_t;
-  friend class rtc_t;
+  friend class clint_t;
   friend class extension_t;
 
   void parse_isa_string(const char* isa);