X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.h;h=6e8d684ae573adb2220041c6ac4a835787475e83;hb=4f8b6a69484bd901f213d9a73ea29d26c8022dfd;hp=ea9cb7bab59efc0c598543f0ec290972ebb5d0d1;hpb=12b772563a33b6c6c3da0343fbfc747b1eeea6b6;p=riscv-isa-sim.git

diff --git a/riscv/processor.h b/riscv/processor.h
index ea9cb7b..6e8d684 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -8,6 +8,7 @@
 #include <string>
 #include <vector>
 #include <map>
+#include "debug_rom/debug_rom_defines.h"
 
 class processor_t;
 class mmu_t;
@@ -193,12 +194,6 @@ public:
   bool slow_path();
   bool halted() { return state.dcsr.cause ? true : false; }
   bool halt_request;
-  // The unique debug rom address that this hart jumps to when entering debug
-  // mode. Rely on the fact that spike hart IDs start at 0 and are consecutive.
-  uint32_t debug_rom_entry() {
-    fprintf(stderr, "Debug_rom_entry called for id %d = %x\n", id, DEBUG_ROM_ENTRY + 4*id);
-    return DEBUG_ROM_ENTRY + 4 * id;
-  }
 
   // Return the index of a trigger that matched, or -1.
   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)