X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.h;h=ace86f963959145e3e8a7227f4fa2e91f0395e71;hb=7e35a2a62f7433060e2ab1c98b3afd8b8a69b829;hp=51fe8d2c8eb81a19be09c4674327c9df48d55e80;hpb=4a97a05a6e806f7abcb6cd30685093aa5b9331a9;p=riscv-isa-sim.git

diff --git a/riscv/processor.h b/riscv/processor.h
index 51fe8d2..ace86f9 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -86,7 +86,7 @@ typedef struct
 // architectural state of a RISC-V hart
 struct state_t
 {
-  void reset();
+  void reset(reg_t max_isa);
 
   static const int num_triggers = 4;
 
@@ -96,6 +96,7 @@ struct state_t
 
   // control and status registers
   reg_t prv;    // TODO: Can this be an enum instead?
+  reg_t misa;
   reg_t mstatus;
   reg_t mepc;
   reg_t mtval;
@@ -185,7 +186,7 @@ public:
   extension_t* get_extension() { return ext; }
   bool supports_extension(unsigned char ext) {
     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
-    return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
+    return ext >= 'A' && ext <= 'Z' && ((state.misa >> (ext - 'A')) & 1);
   }
   void check_pc_alignment(reg_t pc) {
     if (unlikely(pc & 2) && !supports_extension('C'))
@@ -302,7 +303,6 @@ private:
   uint32_t id;
   unsigned max_xlen;
   unsigned xlen;
-  reg_t isa;
   reg_t max_isa;
   std::string isa_string;
   bool histogram_enabled;