X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fprocessor.h;h=ace86f963959145e3e8a7227f4fa2e91f0395e71;hb=7e35a2a62f7433060e2ab1c98b3afd8b8a69b829;hp=7d504d9f5025fa8753b216ebe82bdcac6fa9c2e1;hpb=bdd229b9ea9a78f2fe5d4af1d0a49cf50484aa86;p=riscv-isa-sim.git

diff --git a/riscv/processor.h b/riscv/processor.h
index 7d504d9..ace86f9 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -86,7 +86,7 @@ typedef struct
 // architectural state of a RISC-V hart
 struct state_t
 {
-  void reset();
+  void reset(reg_t max_isa);
 
   static const int num_triggers = 4;