X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Friscv.mk.in;h=80755e711c181794e3ea9cb96ea40443d06e1d2b;hb=d6fcfdebf6a893bf37670fd67203d18653df4a0e;hp=239beb962b7dbeb7898a102bace1a631732db317;hpb=b0f3ed6e3bc78f11371864a0587d918c547b8022;p=riscv-isa-sim.git

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 239beb9..80755e7 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -7,29 +7,36 @@ riscv_subproject_deps = \
 riscv_install_prog_srcs = \
 
 riscv_hdrs = \
-	htif.h \
 	common.h \
 	decode.h \
+	devices.h \
 	disasm.h \
+	dts.h \
 	mmu.h \
 	processor.h \
 	sim.h \
+	simif.h \
 	trap.h \
 	encoding.h \
 	cachesim.h \
 	memtracer.h \
+	tracer.h \
 	extension.h \
 	rocc.h \
 	insn_template.h \
 	mulhi.h \
+	debug_module.h \
+	debug_rom_defines.h \
+	remote_bitbang.h \
+	jtag_dtm.h \
 
 riscv_precompiled_hdrs = \
 	insn_template.h \
 
 riscv_srcs = \
-	htif.cc \
 	processor.cc \
 	execute.cc \
+	dts.cc \
 	sim.cc \
 	interactive.cc \
 	trap.cc \
@@ -40,6 +47,12 @@ riscv_srcs = \
 	extensions.cc \
 	rocc.cc \
 	regnames.cc \
+	devices.cc \
+	rom.cc \
+	clint.cc \
+	debug_module.cc \
+	remote_bitbang.cc \
+	jtag_dtm.cc \
 	$(riscv_gen_srcs) \
 
 riscv_test_srcs =
@@ -107,10 +120,8 @@ riscv_insn_list = \
 	c_lwsp \
 	c_mv \
 	c_or \
-	c_sll \
 	c_slli \
 	c_srai \
-	c_srl \
 	c_srli \
 	c_sub \
 	c_subw \
@@ -127,71 +138,105 @@ riscv_insn_list = \
 	divu \
 	divuw \
 	divw \
+	dret \
+	ebreak \
+	ecall \
 	fadd_d \
+	fadd_q \
 	fadd_s \
 	fclass_d \
+	fclass_q \
 	fclass_s \
 	fcvt_d_l \
 	fcvt_d_lu \
+	fcvt_d_q \
 	fcvt_d_s \
 	fcvt_d_w \
 	fcvt_d_wu \
 	fcvt_l_d \
+	fcvt_l_q \
 	fcvt_l_s \
 	fcvt_lu_d \
+	fcvt_lu_q \
 	fcvt_lu_s \
+	fcvt_q_d \
+	fcvt_q_l \
+	fcvt_q_lu \
+	fcvt_q_s \
+	fcvt_q_w \
+	fcvt_q_wu \
 	fcvt_s_d \
 	fcvt_s_l \
 	fcvt_s_lu \
+	fcvt_s_q \
 	fcvt_s_w \
 	fcvt_s_wu \
 	fcvt_w_d \
+	fcvt_w_q \
 	fcvt_w_s \
 	fcvt_wu_d \
+	fcvt_wu_q \
 	fcvt_wu_s \
 	fdiv_d \
+	fdiv_q \
 	fdiv_s \
 	fence \
 	fence_i \
 	feq_d \
+	feq_q \
 	feq_s \
 	fld \
 	fle_d \
+	fle_q \
 	fle_s \
+	flq \
 	flt_d \
+	flt_q \
 	flt_s \
 	flw \
 	fmadd_d \
+	fmadd_q \
 	fmadd_s \
 	fmax_d \
+	fmax_q \
 	fmax_s \
 	fmin_d \
+	fmin_q \
 	fmin_s \
 	fmsub_d \
+	fmsub_q \
 	fmsub_s \
 	fmul_d \
+	fmul_q \
 	fmul_s \
 	fmv_d_x \
-	fmv_s_x \
+	fmv_w_x \
 	fmv_x_d \
-	fmv_x_s \
+	fmv_x_w \
 	fnmadd_d \
+	fnmadd_q \
 	fnmadd_s \
 	fnmsub_d \
+	fnmsub_q \
 	fnmsub_s \
 	fsd \
 	fsgnj_d \
+	fsgnj_q \
 	fsgnjn_d \
+	fsgnjn_q \
 	fsgnjn_s \
 	fsgnj_s \
 	fsgnjx_d \
+	fsgnjx_q \
 	fsgnjx_s \
+	fsq \
 	fsqrt_d \
+	fsqrt_q \
 	fsqrt_s \
 	fsub_d \
+	fsub_q \
 	fsub_s \
 	fsw \
-	hrts \
 	jal \
 	jalr \
 	lb \
@@ -204,8 +249,7 @@ riscv_insn_list = \
 	lui \
 	lw \
 	lwu \
-	mrth \
-	mrts \
+	mret \
 	mul \
 	mulh \
 	mulhsu \
@@ -218,12 +262,10 @@ riscv_insn_list = \
 	remuw \
 	remw \
 	sb \
-	sbreak \
-	scall \
 	sc_d \
 	sc_w \
 	sd \
-	sfence_vm \
+	sfence_vma \
 	sh \
 	sll \
 	slli \