X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Friscv.mk.in;h=80755e711c181794e3ea9cb96ea40443d06e1d2b;hb=d6fcfdebf6a893bf37670fd67203d18653df4a0e;hp=ada62d5c0c85fbc7cc778d949b50b90a8ee5d758;hpb=01c01cc36f006cfb03cd6d1c5a68f926b93f7787;p=riscv-isa-sim.git

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index ada62d5..80755e7 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -1,23 +1,313 @@
-riscv_subproject_deps =
+get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
+get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
+
+riscv_subproject_deps = \
+	softfloat \
+
+riscv_install_prog_srcs = \
 
 riscv_hdrs = \
 	common.h \
 	decode.h \
-	execute.h \
-	load_elf.h \
+	devices.h \
+	disasm.h \
+	dts.h \
 	mmu.h \
 	processor.h \
 	sim.h \
+	simif.h \
 	trap.h \
-	insns/*.h \
+	encoding.h \
+	cachesim.h \
+	memtracer.h \
+	tracer.h \
+	extension.h \
+	rocc.h \
+	insn_template.h \
+	mulhi.h \
+	debug_module.h \
+	debug_rom_defines.h \
+	remote_bitbang.h \
+	jtag_dtm.h \
+
+riscv_precompiled_hdrs = \
+	insn_template.h \
 
 riscv_srcs = \
-	load_elf.cc \
 	processor.cc \
+	execute.cc \
+	dts.cc \
 	sim.cc \
+	interactive.cc \
 	trap.cc \
+	cachesim.cc \
+	mmu.cc \
+	disasm.cc \
+	extension.cc \
+	extensions.cc \
+	rocc.cc \
+	regnames.cc \
+	devices.cc \
+	rom.cc \
+	clint.cc \
+	debug_module.cc \
+	remote_bitbang.cc \
+	jtag_dtm.cc \
+	$(riscv_gen_srcs) \
 
 riscv_test_srcs =
 
-riscv_install_prog_srcs = \
-	riscv-isa-run.cc \
+riscv_gen_hdrs = \
+	icache.h \
+	insn_list.h \
+
+riscv_insn_list = \
+	add \
+	addi \
+	addiw \
+	addw \
+	amoadd_d \
+	amoadd_w \
+	amoand_d \
+	amoand_w \
+	amomax_d \
+	amomaxu_d \
+	amomaxu_w \
+	amomax_w \
+	amomin_d \
+	amominu_d \
+	amominu_w \
+	amomin_w \
+	amoor_d \
+	amoor_w \
+	amoswap_d \
+	amoswap_w \
+	amoxor_d \
+	amoxor_w \
+	and \
+	andi \
+	auipc \
+	beq \
+	bge \
+	bgeu \
+	blt \
+	bltu \
+	bne \
+	c_add \
+	c_addi4spn \
+	c_addi \
+	c_addw \
+	c_and \
+	c_andi \
+	c_beqz \
+	c_bnez \
+	c_ebreak \
+	c_fld \
+	c_fldsp \
+	c_flw \
+	c_flwsp \
+	c_fsd \
+	c_fsdsp \
+	c_fsw \
+	c_fswsp \
+	c_jal \
+	c_jalr \
+	c_j \
+	c_jr \
+	c_li \
+	c_lui \
+	c_lw \
+	c_lwsp \
+	c_mv \
+	c_or \
+	c_slli \
+	c_srai \
+	c_srli \
+	c_sub \
+	c_subw \
+	c_xor \
+	csrrc \
+	csrrci \
+	csrrs \
+	csrrsi \
+	csrrw \
+	csrrwi \
+	c_sw \
+	c_swsp \
+	div \
+	divu \
+	divuw \
+	divw \
+	dret \
+	ebreak \
+	ecall \
+	fadd_d \
+	fadd_q \
+	fadd_s \
+	fclass_d \
+	fclass_q \
+	fclass_s \
+	fcvt_d_l \
+	fcvt_d_lu \
+	fcvt_d_q \
+	fcvt_d_s \
+	fcvt_d_w \
+	fcvt_d_wu \
+	fcvt_l_d \
+	fcvt_l_q \
+	fcvt_l_s \
+	fcvt_lu_d \
+	fcvt_lu_q \
+	fcvt_lu_s \
+	fcvt_q_d \
+	fcvt_q_l \
+	fcvt_q_lu \
+	fcvt_q_s \
+	fcvt_q_w \
+	fcvt_q_wu \
+	fcvt_s_d \
+	fcvt_s_l \
+	fcvt_s_lu \
+	fcvt_s_q \
+	fcvt_s_w \
+	fcvt_s_wu \
+	fcvt_w_d \
+	fcvt_w_q \
+	fcvt_w_s \
+	fcvt_wu_d \
+	fcvt_wu_q \
+	fcvt_wu_s \
+	fdiv_d \
+	fdiv_q \
+	fdiv_s \
+	fence \
+	fence_i \
+	feq_d \
+	feq_q \
+	feq_s \
+	fld \
+	fle_d \
+	fle_q \
+	fle_s \
+	flq \
+	flt_d \
+	flt_q \
+	flt_s \
+	flw \
+	fmadd_d \
+	fmadd_q \
+	fmadd_s \
+	fmax_d \
+	fmax_q \
+	fmax_s \
+	fmin_d \
+	fmin_q \
+	fmin_s \
+	fmsub_d \
+	fmsub_q \
+	fmsub_s \
+	fmul_d \
+	fmul_q \
+	fmul_s \
+	fmv_d_x \
+	fmv_w_x \
+	fmv_x_d \
+	fmv_x_w \
+	fnmadd_d \
+	fnmadd_q \
+	fnmadd_s \
+	fnmsub_d \
+	fnmsub_q \
+	fnmsub_s \
+	fsd \
+	fsgnj_d \
+	fsgnj_q \
+	fsgnjn_d \
+	fsgnjn_q \
+	fsgnjn_s \
+	fsgnj_s \
+	fsgnjx_d \
+	fsgnjx_q \
+	fsgnjx_s \
+	fsq \
+	fsqrt_d \
+	fsqrt_q \
+	fsqrt_s \
+	fsub_d \
+	fsub_q \
+	fsub_s \
+	fsw \
+	jal \
+	jalr \
+	lb \
+	lbu \
+	ld \
+	lh \
+	lhu \
+	lr_d \
+	lr_w \
+	lui \
+	lw \
+	lwu \
+	mret \
+	mul \
+	mulh \
+	mulhsu \
+	mulhu \
+	mulw \
+	or \
+	ori \
+	rem \
+	remu \
+	remuw \
+	remw \
+	sb \
+	sc_d \
+	sc_w \
+	sd \
+	sfence_vma \
+	sh \
+	sll \
+	slli \
+	slliw \
+	sllw \
+	slt \
+	slti \
+	sltiu \
+	sltu \
+	sra \
+	srai \
+	sraiw \
+	sraw \
+	sret \
+	srl \
+	srli \
+	srliw \
+	srlw \
+	sub \
+	subw \
+	sw \
+	wfi \
+	xor \
+	xori \
+
+riscv_gen_srcs = \
+	$(addsuffix .cc,$(riscv_insn_list))
+
+icache_entries := `grep "ICACHE_ENTRIES =" $(src_dir)/riscv/mmu.h | sed 's/.* = \(.*\);/\1/'`
+
+icache.h: mmu.h
+	$(src_dir)/riscv/gen_icache $(icache_entries) > $@.tmp
+	mv $@.tmp $@
+
+insn_list.h: $(src_dir)/riscv/riscv.mk.in
+	for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \
+		printf 'DEFINE_INSN(%s)\n' "$${insn}" ; \
+	done > $@.tmp
+	mv $@.tmp $@
+
+$(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
+	sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
+
+riscv_junk = \
+	$(riscv_gen_srcs) \