X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.cc;h=0e38c53fa96444a263f1560cbf631e21edc45497;hb=aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e;hp=c503ccbb922bf150f4c9f01da00193acef31c9b4;hpb=46f2fb1d9e33b4cf98c2cc15c2a2da14f0e3580d;p=riscv-isa-sim.git diff --git a/riscv/sim.cc b/riscv/sim.cc index c503ccb..0e38c53 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -1,308 +1,366 @@ +// See LICENSE for license details. + #include "sim.h" -#include "applink.h" -#include "common.h" -#include +#include "mmu.h" +#include "remote_bitbang.h" #include #include +#include #include +#include +#include +#include +#include +#include +#include + +volatile bool ctrlc_pressed = false; +static void handle_signal(int sig) +{ + if (ctrlc_pressed) + exit(-1); + ctrlc_pressed = true; + signal(sig, &handle_signal); +} -sim_t::sim_t(int _nprocs, size_t _memsz, appserver_link_t* _applink, icsim_t* default_icache, icsim_t* default_dcache) - : applink(_applink), - memsz(_memsz), - mem((char*)mmap64(NULL, memsz, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0)), - procs(std::vector(_nprocs,processor_t(this,mem,memsz))) +sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, + std::vector> mems, + const std::vector& args, + std::vector const hartids, unsigned progsize, + unsigned max_bus_master_bits, bool require_authentication) + : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))), + start_pc(start_pc), current_step(0), current_proc(0), debug(false), + remote_bitbang(NULL), + debug_module(this, progsize, max_bus_master_bits, require_authentication) { - demand(mem != MAP_FAILED, "couldn't allocate target machine's memory"); + signal(SIGINT, &handle_signal); - for(int i = 0; i < (int)procs.size(); i++) - procs[i].init(i, default_icache, default_dcache); + for (auto& x : mems) + bus.add_device(x.first, x.second); - applink->init(this); -} + debug_module.add_device(&bus); -sim_t::~sim_t() -{ + debug_mmu = new mmu_t(this, NULL); + + if (hartids.size() == 0) { + for (size_t i = 0; i < procs.size(); i++) { + procs[i] = new processor_t(isa, this, i, halted); + } + } + else { + if (hartids.size() != procs.size()) { + std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl; + exit(1); + } + for (size_t i = 0; i < procs.size(); i++) { + procs[i] = new processor_t(isa, this, hartids[i], halted); + } + } + + clint.reset(new clint_t(procs)); + bus.add_device(CLINT_BASE, clint.get()); } -void sim_t::set_tohost(reg_t val) +sim_t::~sim_t() { - fromhost = 0; - tohost = val; - applink->wait_for_tohost(); + for (size_t i = 0; i < procs.size(); i++) + delete procs[i]; + delete debug_mmu; } -reg_t sim_t::get_fromhost() +void sim_thread_main(void* arg) { - applink->wait_for_fromhost(); - return fromhost; + ((sim_t*)arg)->main(); } -void sim_t::run(bool debug) +void sim_t::main() { - applink->wait_for_start(); + if (!debug && log) + set_procs_debug(true); - while(1) + while (!done()) { - if(!debug) - step_all(100,100,false); + if (debug || ctrlc_pressed) + interactive(); else - { - putchar(':'); - char s[128]; - std::cin.getline(s,sizeof(s)-1); - - char* p = strtok(s," "); - if(!p) - { - interactive_run_noisy(std::string("r"), std::vector(1,"1")); - continue; - } - std::string cmd = p; - - std::vector args; - while((p = strtok(NULL," "))) - args.push_back(p); - - - typedef void (sim_t::*interactive_func)(const std::string&, const std::vector&); - std::map funcs; - - funcs["r"] = &sim_t::interactive_run_noisy; - funcs["rs"] = &sim_t::interactive_run_silent; - funcs["rp"] = &sim_t::interactive_run_proc_noisy; - funcs["rps"] = &sim_t::interactive_run_proc_silent; - funcs["reg"] = &sim_t::interactive_reg; - funcs["fregs"] = &sim_t::interactive_fregs; - funcs["fregd"] = &sim_t::interactive_fregd; - funcs["mem"] = &sim_t::interactive_mem; - funcs["str"] = &sim_t::interactive_str; - funcs["until"] = &sim_t::interactive_until; - funcs["while"] = &sim_t::interactive_until; - funcs["q"] = &sim_t::interactive_quit; - - try - { - if(funcs.count(cmd)) - (this->*funcs[cmd])(cmd, args); - } - catch(trap_t t) {} + step(INTERLEAVE); + if (remote_bitbang) { + remote_bitbang->tick(); } } } -void sim_t::step_all(size_t n, size_t interleave, bool noisy) +int sim_t::run() { - for(size_t j = 0; j < n; j+=interleave) - for(int i = 0; i < (int)procs.size(); i++) - procs[i].step(interleave,noisy); + host = context_t::current(); + target.init(sim_thread_main, this); + return htif_t::run(); } -void sim_t::interactive_run_noisy(const std::string& cmd, const std::vector& args) +void sim_t::step(size_t n) { - interactive_run(cmd,args,true); -} + for (size_t i = 0, steps = 0; i < n; i += steps) + { + steps = std::min(n - i, INTERLEAVE - current_step); + procs[current_proc]->step(steps); -void sim_t::interactive_run_silent(const std::string& cmd, const std::vector& args) -{ - interactive_run(cmd,args,false); + current_step += steps; + if (current_step == INTERLEAVE) + { + current_step = 0; + procs[current_proc]->yield_load_reservation(); + if (++current_proc == procs.size()) { + current_proc = 0; + clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK); + } + + host->switch_to(); + } + } } -void sim_t::interactive_run(const std::string& cmd, const std::vector& args, bool noisy) +void sim_t::set_debug(bool value) { - if(args.size()) - step_all(atoll(args[0].c_str()),1,noisy); - else - while(1) step_all(1,1,noisy); + debug = value; } -void sim_t::interactive_run_proc_noisy(const std::string& cmd, const std::vector& args) +void sim_t::set_log(bool value) { - interactive_run_proc(cmd,args,true); + log = value; } -void sim_t::interactive_run_proc_silent(const std::string& cmd, const std::vector& args) +void sim_t::set_histogram(bool value) { - interactive_run_proc(cmd,args,false); + histogram_enabled = value; + for (size_t i = 0; i < procs.size(); i++) { + procs[i]->set_histogram(histogram_enabled); + } } -void sim_t::interactive_run_proc(const std::string& cmd, const std::vector& a, bool noisy) +void sim_t::set_procs_debug(bool value) { - if(a.size() == 0) - return; - - int p = atoi(a[0].c_str()); - if(p >= (int)procs.size()) - return; - - if(a.size() == 2) - procs[p].step(atoi(a[1].c_str()),noisy); - else - while(1) procs[p].step(1,noisy); + for (size_t i=0; i< procs.size(); i++) + procs[i]->set_debug(value); } -void sim_t::interactive_quit(const std::string& cmd, const std::vector& args) +bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) { - throw quit_sim(); + if (addr + len < addr) + return false; + return bus.load(addr, len, bytes); } -reg_t sim_t::get_pc(const std::vector& args) +bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) { - if(args.size() != 1) - throw trap_illegal_instruction; - - int p = atoi(args[0].c_str()); - if(p >= (int)procs.size()) - throw trap_illegal_instruction; - - return procs[p].pc; + if (addr + len < addr) + return false; + return bus.store(addr, len, bytes); } -reg_t sim_t::get_reg(const std::vector& args) +static std::string dts_compile(const std::string& dts) { - if(args.size() != 2) - throw trap_illegal_instruction; + // Convert the DTS to DTB + int dts_pipe[2]; + pid_t dts_pid; - int p = atoi(args[0].c_str()); - int r = atoi(args[1].c_str()); - if(p >= (int)procs.size() || r >= NXPR) - throw trap_illegal_instruction; + if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) { + std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl; + exit(1); + } - return procs[p].XPR[r]; -} + // Child process to output dts + if (dts_pid == 0) { + close(dts_pipe[0]); + int step, len = dts.length(); + const char *buf = dts.c_str(); + for (int done = 0; done < len; done += step) { + step = write(dts_pipe[1], buf+done, len-done); + if (step == -1) { + std::cerr << "Failed to write dts: " << strerror(errno) << std::endl; + exit(1); + } + } + close(dts_pipe[1]); + exit(0); + } -reg_t sim_t::get_freg(const std::vector& args) -{ - if(args.size() != 2) - throw trap_illegal_instruction; + pid_t dtb_pid; + int dtb_pipe[2]; + if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) { + std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl; + exit(1); + } - int p = atoi(args[0].c_str()); - int r = atoi(args[1].c_str()); - if(p >= (int)procs.size() || r >= NFPR) - throw trap_illegal_instruction; + // Child process to output dtb + if (dtb_pid == 0) { + dup2(dts_pipe[0], 0); + dup2(dtb_pipe[1], 1); + close(dts_pipe[0]); + close(dts_pipe[1]); + close(dtb_pipe[0]); + close(dtb_pipe[1]); + execl(DTC, DTC, "-O", "dtb", 0); + std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl; + exit(1); + } - return procs[p].FPR[r]; -} + close(dts_pipe[1]); + close(dts_pipe[0]); + close(dtb_pipe[1]); -reg_t sim_t::get_tohost(const std::vector& args) -{ - if(args.size() != 1) - throw trap_illegal_instruction; + // Read-out dtb + std::stringstream dtb; - int p = atoi(args[0].c_str()); - if(p >= (int)procs.size()) - throw trap_illegal_instruction; + int got; + char buf[4096]; + while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) { + dtb.write(buf, got); + } + if (got == -1) { + std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl; + exit(1); + } + close(dtb_pipe[0]); + + // Reap children + int status; + waitpid(dts_pid, &status, 0); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + std::cerr << "Child dts process failed" << std::endl; + exit(1); + } + waitpid(dtb_pid, &status, 0); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + std::cerr << "Child dtb process failed" << std::endl; + exit(1); + } - return procs[p].tohost; + return dtb.str(); } -void sim_t::interactive_reg(const std::string& cmd, const std::vector& args) +void sim_t::make_dtb() { - printf("0x%016llx\n",(unsigned long long)get_reg(args)); + const int reset_vec_size = 8; + + start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc; + + uint32_t reset_vec[reset_vec_size] = { + 0x297, // auipc t0,0x0 + 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb + 0xf1402573, // csrr a0, mhartid + get_core(0)->xlen == 32 ? + 0x0182a283u : // lw t0,24(t0) + 0x0182b283u, // ld t0,24(t0) + 0x28067, // jr t0 + 0, + (uint32_t) (start_pc & 0xffffffff), + (uint32_t) (start_pc >> 32) + }; + + std::vector rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); + + std::stringstream s; + s << std::dec << + "/dts-v1/;\n" + "\n" + "/ {\n" + " #address-cells = <2>;\n" + " #size-cells = <2>;\n" + " compatible = \"ucbbar,spike-bare-dev\";\n" + " model = \"ucbbar,spike-bare\";\n" + " cpus {\n" + " #address-cells = <1>;\n" + " #size-cells = <0>;\n" + " timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n"; + for (size_t i = 0; i < procs.size(); i++) { + s << " CPU" << i << ": cpu@" << i << " {\n" + " device_type = \"cpu\";\n" + " reg = <" << i << ">;\n" + " status = \"okay\";\n" + " compatible = \"riscv\";\n" + " riscv,isa = \"" << procs[i]->isa_string << "\";\n" + " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n" + " clock-frequency = <" << CPU_HZ << ">;\n" + " CPU" << i << "_intc: interrupt-controller {\n" + " #interrupt-cells = <1>;\n" + " interrupt-controller;\n" + " compatible = \"riscv,cpu-intc\";\n" + " };\n" + " };\n"; + } + s << " };\n"; + for (auto& m : mems) { + s << std::hex << + " memory@" << m.first << " {\n" + " device_type = \"memory\";\n" + " reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) << + " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n" + " };\n"; + } + s << " soc {\n" + " #address-cells = <2>;\n" + " #size-cells = <2>;\n" + " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n" + " ranges;\n" + " clint@" << CLINT_BASE << " {\n" + " compatible = \"riscv,clint0\";\n" + " interrupts-extended = <" << std::dec; + for (size_t i = 0; i < procs.size(); i++) + s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 "; + reg_t clintbs = CLINT_BASE; + reg_t clintsz = CLINT_SIZE; + s << std::hex << ">;\n" + " reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) << + " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n" + " };\n" + " };\n" + " htif {\n" + " compatible = \"ucb,htif0\";\n" + " };\n" + "};\n"; + + dts = s.str(); + std::string dtb = dts_compile(dts); + + rom.insert(rom.end(), dtb.begin(), dtb.end()); + const int align = 0x1000; + rom.resize((rom.size() + align - 1) / align * align); + + boot_rom.reset(new rom_device_t(rom)); + bus.add_device(DEFAULT_RSTVEC, boot_rom.get()); } -union fpr -{ - reg_t r; - float s; - double d; -}; - -void sim_t::interactive_fregs(const std::string& cmd, const std::vector& args) -{ - fpr f; - f.r = get_freg(args); - printf("%g\n",f.s); +char* sim_t::addr_to_mem(reg_t addr) { + auto desc = bus.find_device(addr); + if (auto mem = dynamic_cast(desc.second)) + if (addr - desc.first < mem->size()) + return mem->contents() + (addr - desc.first); + return NULL; } -void sim_t::interactive_fregd(const std::string& cmd, const std::vector& args) -{ - fpr f; - f.r = get_freg(args); - printf("%g\n",f.d); -} +// htif -reg_t sim_t::get_mem(const std::vector& args) +void sim_t::reset() { - if(args.size() != 1) - throw trap_illegal_instruction; - - reg_t addr = strtol(args[0].c_str(),NULL,16), val; - if(addr == LONG_MAX) - addr = strtoul(args[0].c_str(),NULL,16); - - mmu_t mmu(mem,memsz); - switch(addr % 8) - { - case 0: - val = mmu.load_uint64(addr); - break; - case 4: - val = mmu.load_uint32(addr); - break; - case 2: - case 6: - val = mmu.load_uint16(addr); - break; - default: - val = mmu.load_uint8(addr); - break; - } - return val; + make_dtb(); } -void sim_t::interactive_mem(const std::string& cmd, const std::vector& args) +void sim_t::idle() { - printf("0x%016llx\n",(unsigned long long)get_mem(args)); + target.switch_to(); } -void sim_t::interactive_str(const std::string& cmd, const std::vector& args) +void sim_t::read_chunk(addr_t taddr, size_t len, void* dst) { - if(args.size() != 1) - throw trap_illegal_instruction; - - reg_t addr = strtol(args[0].c_str(),NULL,16); - - mmu_t mmu(mem,memsz); - char ch; - - while((ch = mmu.load_uint8(addr++))) - putchar(ch); - - putchar('\n'); + assert(len == 8); + auto data = debug_mmu->load_uint64(taddr); + memcpy(dst, &data, sizeof data); } -void sim_t::interactive_until(const std::string& cmd, const std::vector& args) +void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) { - if(args.size() < 3) - return; - - std::string scmd = args[0]; - reg_t val = strtol(args[args.size()-1].c_str(),NULL,16); - if(val == LONG_MAX) - val = strtoul(args[args.size()-1].c_str(),NULL,16); - - std::vector args2; - args2 = std::vector(args.begin()+1,args.end()-1); - - while(1) - { - reg_t current; - if(scmd == "reg") - current = get_reg(args2); - else if(scmd == "pc") - current = get_pc(args2); - else if(scmd == "mem") - current = get_mem(args2); - else if(scmd == "tohost") - current = get_tohost(args2); - else - return; - - if(cmd == "until" && current == val) - break; - if(cmd == "while" && current != val) - break; - - step_all(1,1,false); - } + assert(len == 8); + uint64_t data; + memcpy(&data, src, sizeof data); + debug_mmu->store_uint64(taddr, data); }