X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.cc;h=66bebb3b8cbf7bffe61ddba9fd226cf63bd9a7bc;hb=b16ef94394e8f04f11241c2acfe442b4ddbc6853;hp=eb31f12d3b3a288c2311987959fecc1f550132aa;hpb=8abe4c630910b98df7e8f96118d21216e0bc1c30;p=riscv-isa-sim.git

diff --git a/riscv/sim.cc b/riscv/sim.cc
index eb31f12..66bebb3 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -71,6 +71,8 @@ reg_t sim_t::get_scr(int which)
 
 int sim_t::run()
 {
+  if (!debug && log)
+    set_procs_debug(true);
   while (htif->tick())
   {
     if (debug || ctrlc_pressed)
@@ -123,6 +125,11 @@ void sim_t::set_debug(bool value)
   debug = value;
 }
 
+void sim_t::set_log(bool value)
+{
+  log = value;
+}
+
 void sim_t::set_histogram(bool value)
 {
   histogram_enabled = value;