X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.cc;h=793a2c871e6267439c88b1a5c2da7d289495c232;hb=f8a83a80525264761a982cdb4074cb09ac72d7de;hp=461ae6ac211fb2d4e9420b91da4899e53613b5cf;hpb=8a09a059dc3ddd0b6df8028ae7e4c9e6e1c9d41e;p=riscv-isa-sim.git diff --git a/riscv/sim.cc b/riscv/sim.cc index 461ae6a..793a2c8 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -10,6 +10,9 @@ #include #include #include +#include +#include +#include volatile bool ctrlc_pressed = false; static void handle_signal(int sig) @@ -20,37 +23,39 @@ static void handle_signal(int sig) signal(sig, &handle_signal); } -sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, - const std::vector& args) - : htif_t(args), debug_module(this), procs(std::max(nprocs, size_t(1))), +sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, + std::vector> mems, + const std::vector& args, std::vector const hartids) + : htif_t(args), debug_module(this), mems(mems), procs(std::max(nprocs, size_t(1))), + start_pc(start_pc), current_step(0), current_proc(0), debug(false), remote_bitbang(NULL) { signal(SIGINT, &handle_signal); - // allocate target machine's memory, shrinking it as necessary - // until the allocation succeeds - size_t memsz0 = (size_t)mem_mb << 20; - size_t quantum = 1L << 20; - if (memsz0 == 0) - memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20; - memsz = memsz0; - while ((mem = (char*)calloc(1, memsz)) == NULL) - memsz = (size_t)(memsz*0.9)/quantum*quantum; + for (auto& x : mems) + bus.add_device(x.first, x.second); - if (memsz != memsz0) - fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n", - memsz, memsz0); - - bus.add_device(DEBUG_START, &debug_module); + debug_module.add_device(&bus); debug_mmu = new mmu_t(this, NULL); - for (size_t i = 0; i < procs.size(); i++) { - procs[i] = new processor_t(isa, this, i, halted); + if (hartids.size() == 0) { + for (size_t i = 0; i < procs.size(); i++) { + procs[i] = new processor_t(isa, this, i, halted); + } + } + else { + if (hartids.size() != procs.size()) { + std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl; + exit(1); + } + for (size_t i = 0; i < procs.size(); i++) { + procs[i] = new processor_t(isa, this, hartids[i], halted); + } } - rtc.reset(new rtc_t(procs)); - make_config_string(); + clint.reset(new clint_t(procs)); + bus.add_device(CLINT_BASE, clint.get()); } sim_t::~sim_t() @@ -58,7 +63,6 @@ sim_t::~sim_t() for (size_t i = 0; i < procs.size(); i++) delete procs[i]; delete debug_mmu; - free(mem); } void sim_thread_main(void* arg) @@ -104,7 +108,7 @@ void sim_t::step(size_t n) procs[current_proc]->yield_load_reservation(); if (++current_proc == procs.size()) { current_proc = 0; - rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK); + clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK); } host->switch_to(); @@ -150,66 +154,194 @@ bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) return bus.store(addr, len, bytes); } -void sim_t::make_config_string() +static std::string dts_compile(const std::string& dts) { - reg_t rtc_addr = EXT_IO_BASE; - bus.add_device(rtc_addr, rtc.get()); + // Convert the DTS to DTB + int dts_pipe[2]; + pid_t dts_pid; - const int align = 0x1000; - reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align; - reg_t cpu_size = align; - - uint32_t reset_vec[8] = { - 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector - 0x00028067, // jump straight to DRAM_BASE - 0x00000000, // reserved - 0, // config string pointer - 0, 0, 0, 0 // trap vector + if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) { + std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl; + exit(1); + } + + // Child process to output dts + if (dts_pid == 0) { + close(dts_pipe[0]); + int step, len = dts.length(); + const char *buf = dts.c_str(); + for (int done = 0; done < len; done += step) { + step = write(dts_pipe[1], buf+done, len-done); + if (step == -1) { + std::cerr << "Failed to write dts: " << strerror(errno) << std::endl; + exit(1); + } + } + close(dts_pipe[1]); + exit(0); + } + + pid_t dtb_pid; + int dtb_pipe[2]; + if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) { + std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl; + exit(1); + } + + // Child process to output dtb + if (dtb_pid == 0) { + dup2(dts_pipe[0], 0); + dup2(dtb_pipe[1], 1); + close(dts_pipe[0]); + close(dts_pipe[1]); + close(dtb_pipe[0]); + close(dtb_pipe[1]); + execl(DTC, DTC, "-O", "dtb", 0); + std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl; + exit(1); + } + + close(dts_pipe[1]); + close(dts_pipe[0]); + close(dtb_pipe[1]); + + // Read-out dtb + std::stringstream dtb; + + int got; + char buf[4096]; + while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) { + dtb.write(buf, got); + } + if (got == -1) { + std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl; + exit(1); + } + close(dtb_pipe[0]); + + // Reap children + int status; + waitpid(dts_pid, &status, 0); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + std::cerr << "Child dts process failed" << std::endl; + exit(1); + } + waitpid(dtb_pid, &status, 0); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + std::cerr << "Child dtb process failed" << std::endl; + exit(1); + } + + return dtb.str(); +} + +void sim_t::make_dtb() +{ + const int reset_vec_size = 8; + + start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc; + + uint32_t reset_vec[reset_vec_size] = { + 0x297, // auipc t0,0x0 + 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb + 0xf1402573, // csrr a0, mhartid + get_core(0)->xlen == 32 ? + 0x0182a283u : // lw t0,24(t0) + 0x0182b283u, // ld t0,24(t0) + 0x28067, // jr t0 + 0, + (uint32_t) (start_pc & 0xffffffff), + (uint32_t) (start_pc >> 32) }; - reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer std::vector rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); std::stringstream s; - s << std::hex << - "platform {\n" - " vendor ucb;\n" - " arch spike;\n" - "};\n" - "rtc {\n" - " addr 0x" << rtc_addr << ";\n" - "};\n" - "ram {\n" - " 0 {\n" - " addr 0x" << DRAM_BASE << ";\n" - " size 0x" << memsz << ";\n" - " };\n" - "};\n" - "core {\n"; + s << std::dec << + "/dts-v1/;\n" + "\n" + "/ {\n" + " #address-cells = <2>;\n" + " #size-cells = <2>;\n" + " compatible = \"ucbbar,spike-bare-dev\";\n" + " model = \"ucbbar,spike-bare\";\n" + " cpus {\n" + " #address-cells = <1>;\n" + " #size-cells = <0>;\n" + " timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n"; for (size_t i = 0; i < procs.size(); i++) { - s << - " " << i << " {\n" - " " << "0 {\n" << // hart 0 on core i - " isa " << procs[i]->isa_string << ";\n" - " timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n" - " ipi 0x" << cpu_addr << ";\n" - " };\n" - " };\n"; - bus.add_device(cpu_addr, procs[i]); - cpu_addr += cpu_size; + s << " CPU" << i << ": cpu@" << i << " {\n" + " device_type = \"cpu\";\n" + " reg = <" << i << ">;\n" + " status = \"okay\";\n" + " compatible = \"riscv\";\n" + " riscv,isa = \"" << procs[i]->isa_string << "\";\n" + " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n" + " clock-frequency = <" << CPU_HZ << ">;\n" + " CPU" << i << "_intc: interrupt-controller {\n" + " #interrupt-cells = <1>;\n" + " interrupt-controller;\n" + " compatible = \"riscv,cpu-intc\";\n" + " };\n" + " };\n"; } - s << "};\n"; - - config_string = s.str(); - rom.insert(rom.end(), config_string.begin(), config_string.end()); - rom.resize((rom.size() / align + 1) * align); + s << " };\n"; + for (auto& m : mems) { + s << std::hex << + " memory@" << m.first << " {\n" + " device_type = \"memory\";\n" + " reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) << + " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n" + " };\n"; + } + s << " soc {\n" + " #address-cells = <2>;\n" + " #size-cells = <2>;\n" + " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n" + " ranges;\n" + " clint@" << CLINT_BASE << " {\n" + " compatible = \"riscv,clint0\";\n" + " interrupts-extended = <" << std::dec; + for (size_t i = 0; i < procs.size(); i++) + s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 "; + reg_t clintbs = CLINT_BASE; + reg_t clintsz = CLINT_SIZE; + s << std::hex << ">;\n" + " reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) << + " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n" + " };\n" + " };\n" + " htif {\n" + " compatible = \"ucb,htif0\";\n" + " };\n" + "};\n"; + + dts = s.str(); + std::string dtb = dts_compile(dts); + + rom.insert(rom.end(), dtb.begin(), dtb.end()); + const int align = 0x1000; + rom.resize((rom.size() + align - 1) / align * align); boot_rom.reset(new rom_device_t(rom)); bus.add_device(DEFAULT_RSTVEC, boot_rom.get()); } +char* sim_t::addr_to_mem(reg_t addr) { + auto desc = bus.find_device(addr); + if (auto mem = dynamic_cast(desc.second)) + if (addr - desc.first < mem->size()) + return mem->contents() + (addr - desc.first); + return NULL; +} + // htif +void sim_t::reset() +{ + make_dtb(); +} + void sim_t::idle() { target.switch_to();