X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.cc;h=81c5f6f1c465331a470222237f03f0261d661552;hb=9d1e10a36e771bf8cfbf515e07e856e021c1007a;hp=7a10c9b4d2c9a4705cf726c0bd638e242950f7b4;hpb=b04dfe31de85923faf4c701ec2fcf7ff0afc6de7;p=riscv-isa-sim.git diff --git a/riscv/sim.cc b/riscv/sim.cc index 7a10c9b..81c5f6f 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -2,7 +2,7 @@ #include "sim.h" #include "mmu.h" -#include "gdbserver.h" +#include "remote_bitbang.h" #include #include #include @@ -23,39 +23,42 @@ static void handle_signal(int sig) signal(sig, &handle_signal); } -sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, - const std::vector& args) - : htif_t(args), procs(std::max(nprocs, size_t(1))), - current_step(0), current_proc(0), debug(false), gdbserver(NULL) +sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, + std::vector> mems, + const std::vector& args, + std::vector const hartids, unsigned progsize, + unsigned max_bus_master_bits, bool require_authentication) + : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))), + start_pc(start_pc), current_step(0), current_proc(0), debug(false), + remote_bitbang(NULL), + debug_module(this, progsize, max_bus_master_bits, require_authentication) { signal(SIGINT, &handle_signal); - // allocate target machine's memory, shrinking it as necessary - // until the allocation succeeds - size_t memsz0 = (size_t)mem_mb << 20; - size_t quantum = 1L << 20; - if (memsz0 == 0) - memsz0 = (size_t)2048 << 20; - memsz = memsz0; - while ((mem = (char*)calloc(1, memsz)) == NULL) - memsz = (size_t)(memsz*0.9)/quantum*quantum; + for (auto& x : mems) + bus.add_device(x.first, x.second); - if (memsz != memsz0) - fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n", - memsz, memsz0); - - bus.add_device(DEBUG_START, &debug_module); + debug_module.add_device(&bus); debug_mmu = new mmu_t(this, NULL); - for (size_t i = 0; i < procs.size(); i++) { - procs[i] = new processor_t(isa, this, i, halted); + if (hartids.size() == 0) { + for (size_t i = 0; i < procs.size(); i++) { + procs[i] = new processor_t(isa, this, i, halted); + } + } + else { + if (hartids.size() != procs.size()) { + std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl; + exit(1); + } + for (size_t i = 0; i < procs.size(); i++) { + procs[i] = new processor_t(isa, this, hartids[i], halted); + } } clint.reset(new clint_t(procs)); bus.add_device(CLINT_BASE, clint.get()); - - make_dtb(); } sim_t::~sim_t() @@ -63,7 +66,6 @@ sim_t::~sim_t() for (size_t i = 0; i < procs.size(); i++) delete procs[i]; delete debug_mmu; - free(mem); } void sim_thread_main(void* arg) @@ -82,8 +84,8 @@ void sim_t::main() interactive(); else step(INTERLEAVE); - if (gdbserver) { - gdbserver->handle(); + if (remote_bitbang) { + remote_bitbang->tick(); } } } @@ -238,14 +240,22 @@ static std::string dts_compile(const std::string& dts) void sim_t::make_dtb() { - uint32_t reset_vec[] = { - 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // auipc t0, DRAM_BASE - 0x597, // auipc a1, 0 - 0x58593, // addi a1, a1, 0 - 0xf1402573, // csrr a0,mhartid - 0x00028067 // jalr zero, t0, 0 (jump straight to DRAM_BASE) + const int reset_vec_size = 8; + + start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc; + + uint32_t reset_vec[reset_vec_size] = { + 0x297, // auipc t0,0x0 + 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb + 0xf1402573, // csrr a0, mhartid + get_core(0)->get_xlen() == 32 ? + 0x0182a283u : // lw t0,24(t0) + 0x0182b283u, // ld t0,24(t0) + 0x28067, // jr t0 + 0, + (uint32_t) (start_pc & 0xffffffff), + (uint32_t) (start_pc >> 32) }; - reset_vec[2] += (sizeof(reset_vec) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start std::vector rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); @@ -268,8 +278,8 @@ void sim_t::make_dtb() " reg = <" << i << ">;\n" " status = \"okay\";\n" " compatible = \"riscv\";\n" - " riscv,isa = \"" << procs[i]->isa_string << "\";\n" - " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n" + " riscv,isa = \"" << procs[i]->get_isa_string() << "\";\n" + " mmu-type = \"riscv," << (procs[i]->get_max_xlen() <= 32 ? "sv32" : "sv48") << "\";\n" " clock-frequency = <" << CPU_HZ << ">;\n" " CPU" << i << "_intc: interrupt-controller {\n" " #interrupt-cells = <1>;\n" @@ -278,15 +288,16 @@ void sim_t::make_dtb() " };\n" " };\n"; } - reg_t membs = DRAM_BASE; - s << std::hex << - " };\n" - " memory@" << DRAM_BASE << " {\n" + s << " };\n"; + for (auto& m : mems) { + s << std::hex << + " memory@" << m.first << " {\n" " device_type = \"memory\";\n" - " reg = <0x" << (membs >> 32) << " 0x" << (membs & (uint32_t)-1) << - " 0x" << (memsz >> 32) << " 0x" << (memsz & (uint32_t)-1) << ">;\n" - " };\n" - " soc {\n" + " reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) << + " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n" + " };\n"; + } + s << " soc {\n" " #address-cells = <2>;\n" " #size-cells = <2>;\n" " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n" @@ -303,6 +314,9 @@ void sim_t::make_dtb() " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n" " };\n" " };\n" + " htif {\n" + " compatible = \"ucb,htif0\";\n" + " };\n" "};\n"; dts = s.str(); @@ -316,8 +330,21 @@ void sim_t::make_dtb() bus.add_device(DEFAULT_RSTVEC, boot_rom.get()); } +char* sim_t::addr_to_mem(reg_t addr) { + auto desc = bus.find_device(addr); + if (auto mem = dynamic_cast(desc.second)) + if (addr - desc.first < mem->size()) + return mem->contents() + (addr - desc.first); + return NULL; +} + // htif +void sim_t::reset() +{ + make_dtb(); +} + void sim_t::idle() { target.switch_to();