X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.cc;h=a44ced6a832a67950bd4d620b1b66cccde310c15;hb=84e1ac19ed5a69224aa8c3f920e3840fbc670771;hp=033f12bc40983c211e09693037d56fcc8dcc2e26;hpb=773fab34d46e2ddaf4318b851ab23bd813f168ad;p=riscv-isa-sim.git diff --git a/riscv/sim.cc b/riscv/sim.cc index 033f12b..a44ced6 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -10,6 +10,9 @@ #include #include #include +#include +#include +#include volatile bool ctrlc_pressed = false; static void handle_signal(int sig) @@ -31,7 +34,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, size_t memsz0 = (size_t)mem_mb << 20; size_t quantum = 1L << 20; if (memsz0 == 0) - memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20; + memsz0 = (size_t)2048 << 20; memsz = memsz0; while ((mem = (char*)calloc(1, memsz)) == NULL) @@ -49,8 +52,10 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, procs[i] = new processor_t(isa, this, i, halted); } - rtc.reset(new rtc_t(procs)); - make_config_string(); + clint.reset(new clint_t(procs)); + bus.add_device(CLINT_BASE, clint.get()); + + make_dtb(); } sim_t::~sim_t() @@ -104,7 +109,7 @@ void sim_t::step(size_t n) procs[current_proc]->yield_load_reservation(); if (++current_proc == procs.size()) { current_proc = 0; - rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK); + clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK); } host->switch_to(); @@ -150,59 +155,162 @@ bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) return bus.store(addr, len, bytes); } -void sim_t::make_config_string() +static std::string dts_compile(const std::string& dts) { - reg_t rtc_addr = EXT_IO_BASE; - bus.add_device(rtc_addr, rtc.get()); + // Convert the DTS to DTB + int dts_pipe[2]; + pid_t dts_pid; - const int align = 0x1000; - reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align; - reg_t cpu_size = align; - - uint32_t reset_vec[8] = { - 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector - 0x00028067, // jump straight to DRAM_BASE - 0x00000000, // reserved - 0, // config string pointer - 0, 0, 0, 0 // trap vector + if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) { + std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl; + exit(1); + } + + // Child process to output dts + if (dts_pid == 0) { + close(dts_pipe[0]); + int step, len = dts.length(); + const char *buf = dts.c_str(); + for (int done = 0; done < len; done += step) { + step = write(dts_pipe[1], buf+done, len-done); + if (step == -1) { + std::cerr << "Failed to write dts: " << strerror(errno) << std::endl; + exit(1); + } + } + close(dts_pipe[1]); + exit(0); + } + + pid_t dtb_pid; + int dtb_pipe[2]; + if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) { + std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl; + exit(1); + } + + // Child process to output dtb + if (dtb_pid == 0) { + dup2(dts_pipe[0], 0); + dup2(dtb_pipe[1], 1); + close(dts_pipe[0]); + close(dts_pipe[1]); + close(dtb_pipe[0]); + close(dtb_pipe[1]); + execl(DTC, DTC, "-O", "dtb", 0); + std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl; + exit(1); + } + + close(dts_pipe[1]); + close(dts_pipe[0]); + close(dtb_pipe[1]); + + // Read-out dtb + std::stringstream dtb; + + int got; + char buf[4096]; + while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) { + dtb.write(buf, got); + } + if (got == -1) { + std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl; + exit(1); + } + close(dtb_pipe[0]); + + // Reap children + int status; + waitpid(dts_pid, &status, 0); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + std::cerr << "Child dts process failed" << std::endl; + exit(1); + } + waitpid(dtb_pid, &status, 0); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + std::cerr << "Child dtb process failed" << std::endl; + exit(1); + } + + return dtb.str(); +} + +void sim_t::make_dtb() +{ + uint32_t reset_vec[] = { + 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // auipc t0, DRAM_BASE + 0x597, // auipc a1, 0 + 0x58593, // addi a1, a1, 0 + 0xf1402573, // csrr a0,mhartid + 0x00028067 // jalr zero, t0, 0 (jump straight to DRAM_BASE) }; - reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer + reset_vec[2] += (sizeof(reset_vec) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start std::vector rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); std::stringstream s; - s << std::hex << - "platform {\n" - " vendor ucb;\n" - " arch spike;\n" - "};\n" - "rtc {\n" - " addr 0x" << rtc_addr << ";\n" - "};\n" - "ram {\n" - " 0 {\n" - " addr 0x" << DRAM_BASE << ";\n" - " size 0x" << memsz << ";\n" - " };\n" - "};\n" - "core {\n"; + s << std::dec << + "/dts-v1/;\n" + "\n" + "/ {\n" + " #address-cells = <2>;\n" + " #size-cells = <2>;\n" + " compatible = \"ucbbar,spike-bare-dev\";\n" + " model = \"ucbbar,spike-bare\";\n" + " cpus {\n" + " #address-cells = <1>;\n" + " #size-cells = <0>;\n" + " timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n"; for (size_t i = 0; i < procs.size(); i++) { - s << - " " << i << " {\n" - " " << "0 {\n" << // hart 0 on core i - " isa " << procs[i]->isa_string << ";\n" - " timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n" - " ipi 0x" << cpu_addr << ";\n" - " };\n" - " };\n"; - bus.add_device(cpu_addr, procs[i]); - cpu_addr += cpu_size; + s << " CPU" << i << ": cpu@" << i << " {\n" + " device_type = \"cpu\";\n" + " reg = <" << i << ">;\n" + " status = \"okay\";\n" + " compatible = \"riscv\";\n" + " riscv,isa = \"" << procs[i]->isa_string << "\";\n" + " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n" + " clock-frequency = <" << CPU_HZ << ">;\n" + " CPU" << i << "_intc: interrupt-controller {\n" + " #interrupt-cells = <1>;\n" + " interrupt-controller;\n" + " compatible = \"riscv,cpu-intc\";\n" + " };\n" + " };\n"; } - s << "};\n"; - - config_string = s.str(); - rom.insert(rom.end(), config_string.begin(), config_string.end()); - rom.resize((rom.size() / align + 1) * align); + reg_t membs = DRAM_BASE; + s << std::hex << + " };\n" + " memory@" << DRAM_BASE << " {\n" + " device_type = \"memory\";\n" + " reg = <0x" << (membs >> 32) << " 0x" << (membs & (uint32_t)-1) << + " 0x" << (memsz >> 32) << " 0x" << (memsz & (uint32_t)-1) << ">;\n" + " };\n" + " soc {\n" + " #address-cells = <2>;\n" + " #size-cells = <2>;\n" + " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n" + " ranges;\n" + " clint@" << CLINT_BASE << " {\n" + " compatible = \"riscv,clint0\";\n" + " interrupts-extended = <" << std::dec; + for (size_t i = 0; i < procs.size(); i++) + s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 "; + reg_t clintbs = CLINT_BASE; + reg_t clintsz = CLINT_SIZE; + s << std::hex << ">;\n" + " reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) << + " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n" + " };\n" + " };\n" + "};\n"; + + dts = s.str(); + std::string dtb = dts_compile(dts); + + rom.insert(rom.end(), dtb.begin(), dtb.end()); + const int align = 0x1000; + rom.resize((rom.size() + align - 1) / align * align); boot_rom.reset(new rom_device_t(rom)); bus.add_device(DEFAULT_RSTVEC, boot_rom.get());