X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.h;h=6c6e4350702d62b240a42730a20f0b3efbd8f901;hb=aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e;hp=2e7b214fd3a8ec06f8494013e3a0ca778f73de32;hpb=191671a2015136c429394fd3051e4a9c1ff45352;p=riscv-isa-sim.git

diff --git a/riscv/sim.h b/riscv/sim.h
index 2e7b214..6c6e435 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -3,70 +3,68 @@
 #ifndef _RISCV_SIM_H
 #define _RISCV_SIM_H
 
+#include "processor.h"
+#include "devices.h"
+#include "debug_module.h"
+#include <fesvr/htif.h>
+#include <fesvr/context.h>
 #include <vector>
 #include <string>
 #include <memory>
-#include "processor.h"
-#include "devices.h"
-#include "gdbserver.h"
 
-class htif_isasim_t;
 class mmu_t;
+class remote_bitbang_t;
 
 // this class encapsulates the processors and memory in a RISC-V machine.
-class sim_t
+class sim_t : public htif_t
 {
 public:
-  sim_t(const char* isa, size_t _nprocs, size_t mem_mb, bool halted,
-        const std::vector<std::string>& htif_args);
+  sim_t(const char* isa, size_t _nprocs,  bool halted, reg_t start_pc,
+        std::vector<std::pair<reg_t, mem_t*>> mems,
+        const std::vector<std::string>& args, const std::vector<int> hartids,
+        unsigned progsize, unsigned max_bus_master_bits, bool require_authentication);
   ~sim_t();
 
   // run the simulation to completion
   int run();
-  bool running();
   void set_debug(bool value);
   void set_log(bool value);
   void set_histogram(bool value);
   void set_procs_debug(bool value);
-  void set_gdbserver(gdbserver_t* gdbserver) { this->gdbserver = gdbserver; }
-  htif_isasim_t* get_htif() { return htif.get(); }
-  const char* get_config_string() { return config_string.c_str(); }
-
-  // returns the number of processors in this simulator
-  size_t num_cores() { return procs.size(); }
+  void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
+    this->remote_bitbang = remote_bitbang;
+  }
+  const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); }
   processor_t* get_core(size_t i) { return procs.at(i); }
+  unsigned nprocs() const { return procs.size(); }
 
 private:
-  std::unique_ptr<htif_isasim_t> htif;
-  char* mem; // main memory
-  size_t memsz; // memory size in bytes
+  std::vector<std::pair<reg_t, mem_t*>> mems;
   mmu_t* debug_mmu;  // debug port into main memory
   std::vector<processor_t*> procs;
-  std::string config_string;
+  reg_t start_pc;
+  std::string dts;
   std::unique_ptr<rom_device_t> boot_rom;
-  std::unique_ptr<rtc_t> rtc;
+  std::unique_ptr<clint_t> clint;
   bus_t bus;
 
   processor_t* get_core(const std::string& i);
   void step(size_t n); // step through simulation
   static const size_t INTERLEAVE = 5000;
   static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
+  static const size_t CPU_HZ = 1000000000; // 1GHz CPU
   size_t current_step;
   size_t current_proc;
   bool debug;
   bool log;
   bool histogram_enabled; // provide a histogram of PCs
-  gdbserver_t* gdbserver;
+  remote_bitbang_t* remote_bitbang;
 
   // memory-mapped I/O routines
-  bool addr_is_mem(reg_t addr) {
-    return addr >= DRAM_BASE && addr < DRAM_BASE + memsz;
-  }
-  char* addr_to_mem(reg_t addr) { return mem + addr - DRAM_BASE; }
-  reg_t mem_to_addr(char* x) { return x - mem + DRAM_BASE; }
+  char* addr_to_mem(reg_t addr);
   bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
   bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
-  void make_config_string();
+  void make_dtb();
 
   // presents a prompt for introspection into the simulation
   void interactive();
@@ -78,6 +76,7 @@ private:
   void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_freg(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
@@ -85,19 +84,32 @@ private:
   void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
   reg_t get_reg(const std::vector<std::string>& args);
-  reg_t get_freg(const std::vector<std::string>& args);
+  freg_t get_freg(const std::vector<std::string>& args);
   reg_t get_mem(const std::vector<std::string>& args);
   reg_t get_pc(const std::vector<std::string>& args);
 
-  // Return a pointer to Debug RAM in spike address space.
-  char *debug_ram() const {
-      return mem + memsz - DEBUG_SIZE + DEBUG_RAM_START - DEBUG_START;
-  }
-
-  friend class htif_isasim_t;
   friend class processor_t;
   friend class mmu_t;
-  friend class gdbserver_t;
+  friend class debug_module_t;
+
+  // htif
+  friend void sim_thread_main(void*);
+  void main();
+
+  context_t* host;
+  context_t target;
+  void reset();
+  void idle();
+  void read_chunk(addr_t taddr, size_t len, void* dst);
+  void write_chunk(addr_t taddr, size_t len, const void* src);
+  size_t chunk_align() { return 8; }
+  size_t chunk_max_size() { return 8; }
+
+public:
+  // Initialize this after procs, because in debug_module_t::reset() we
+  // enumerate processors, which segfaults if procs hasn't been initialized
+  // yet.
+  debug_module_t debug_module;
 };
 
 extern volatile bool ctrlc_pressed;