X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.h;h=6c6e4350702d62b240a42730a20f0b3efbd8f901;hb=aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e;hp=4cb70b4d47deee29839968be430810be2e75e4d2;hpb=b4de20a92e48e9e08872323675bdd4bbf07b37d6;p=riscv-isa-sim.git diff --git a/riscv/sim.h b/riscv/sim.h index 4cb70b4..6c6e435 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -19,8 +19,10 @@ class remote_bitbang_t; class sim_t : public htif_t { public: - sim_t(const char* isa, size_t _nprocs, size_t mem_mb, bool halted, - const std::vector& args); + sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc, + std::vector> mems, + const std::vector& args, const std::vector hartids, + unsigned progsize, unsigned max_bus_master_bits, bool require_authentication); ~sim_t(); // run the simulation to completion @@ -32,26 +34,25 @@ public: void set_remote_bitbang(remote_bitbang_t* remote_bitbang) { this->remote_bitbang = remote_bitbang; } - const char* get_config_string() { return config_string.c_str(); } + const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } unsigned nprocs() const { return procs.size(); } - debug_module_t debug_module; - private: - char* mem; // main memory - size_t memsz; // memory size in bytes + std::vector> mems; mmu_t* debug_mmu; // debug port into main memory std::vector procs; - std::string config_string; + reg_t start_pc; + std::string dts; std::unique_ptr boot_rom; - std::unique_ptr rtc; + std::unique_ptr clint; bus_t bus; processor_t* get_core(const std::string& i); void step(size_t n); // step through simulation static const size_t INTERLEAVE = 5000; static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core + static const size_t CPU_HZ = 1000000000; // 1GHz CPU size_t current_step; size_t current_proc; bool debug; @@ -60,14 +61,10 @@ private: remote_bitbang_t* remote_bitbang; // memory-mapped I/O routines - bool addr_is_mem(reg_t addr) { - return addr >= DRAM_BASE && addr < DRAM_BASE + memsz; - } - char* addr_to_mem(reg_t addr) { return mem + addr - DRAM_BASE; } - reg_t mem_to_addr(char* x) { return x - mem + DRAM_BASE; } + char* addr_to_mem(reg_t addr); bool mmio_load(reg_t addr, size_t len, uint8_t* bytes); bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes); - void make_config_string(); + void make_dtb(); // presents a prompt for introspection into the simulation void interactive(); @@ -79,6 +76,7 @@ private: void interactive_run_noisy(const std::string& cmd, const std::vector& args); void interactive_run_silent(const std::string& cmd, const std::vector& args); void interactive_reg(const std::string& cmd, const std::vector& args); + void interactive_freg(const std::string& cmd, const std::vector& args); void interactive_fregs(const std::string& cmd, const std::vector& args); void interactive_fregd(const std::string& cmd, const std::vector& args); void interactive_pc(const std::string& cmd, const std::vector& args); @@ -86,12 +84,13 @@ private: void interactive_str(const std::string& cmd, const std::vector& args); void interactive_until(const std::string& cmd, const std::vector& args); reg_t get_reg(const std::vector& args); - reg_t get_freg(const std::vector& args); + freg_t get_freg(const std::vector& args); reg_t get_mem(const std::vector& args); reg_t get_pc(const std::vector& args); friend class processor_t; friend class mmu_t; + friend class debug_module_t; // htif friend void sim_thread_main(void*); @@ -99,12 +98,18 @@ private: context_t* host; context_t target; - void reset() { } + void reset(); void idle(); void read_chunk(addr_t taddr, size_t len, void* dst); void write_chunk(addr_t taddr, size_t len, const void* src); size_t chunk_align() { return 8; } size_t chunk_max_size() { return 8; } + +public: + // Initialize this after procs, because in debug_module_t::reset() we + // enumerate processors, which segfaults if procs hasn't been initialized + // yet. + debug_module_t debug_module; }; extern volatile bool ctrlc_pressed;