X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.h;h=89d3648ee4aa91651d5628d960ccd56ecfa66291;hb=a9c5b05eca6a46a0c8722b26b741fc7f1de22405;hp=6745e75f8e9694db330a990d032ca4ff9151e7b9;hpb=27e29e69cc586a7d97e2ccae2447faa79b66f7b8;p=riscv-isa-sim.git

diff --git a/riscv/sim.h b/riscv/sim.h
index 6745e75..89d3648 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -44,13 +44,14 @@ private:
   mmu_t* debug_mmu;  // debug port into main memory
   std::vector<processor_t*> procs;
   std::unique_ptr<rom_device_t> config_string;
+  std::unique_ptr<rtc_t> rtc;
+  reg_t config_string_addr;
   bus_t bus;
 
   processor_t* get_core(const std::string& i);
   void step(size_t n); // step through simulation
   static const size_t INTERLEAVE = 5000;
   static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
-  reg_t rtc;
   size_t current_step;
   size_t current_proc;
   bool debug;