X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.h;h=97e9edecb8dc08d758a4c4c46bace1127dd670c6;hb=d6fcfdebf6a893bf37670fd67203d18653df4a0e;hp=421f5c2bc3a279c8e6f99bce757b865546d5ecde;hpb=75f2a05df9cdff6f3faba748065b3184b9f01b01;p=riscv-isa-sim.git

diff --git a/riscv/sim.h b/riscv/sim.h
index 421f5c2..97e9ede 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -6,6 +6,7 @@
 #include "processor.h"
 #include "devices.h"
 #include "debug_module.h"
+#include "simif.h"
 #include <fesvr/htif.h>
 #include <fesvr/context.h>
 #include <vector>
@@ -13,15 +14,16 @@
 #include <memory>
 
 class mmu_t;
-class gdbserver_t;
+class remote_bitbang_t;
 
 // this class encapsulates the processors and memory in a RISC-V machine.
-class sim_t : public htif_t
+class sim_t : public htif_t, public simif_t
 {
 public:
   sim_t(const char* isa, size_t _nprocs,  bool halted, reg_t start_pc,
         std::vector<std::pair<reg_t, mem_t*>> mems,
-        const std::vector<std::string>& args);
+        const std::vector<std::string>& args, const std::vector<int> hartids,
+        unsigned progsize, unsigned max_bus_master_bits, bool require_authentication);
   ~sim_t();
 
   // run the simulation to completion
@@ -30,9 +32,15 @@ public:
   void set_log(bool value);
   void set_histogram(bool value);
   void set_procs_debug(bool value);
-  void set_gdbserver(gdbserver_t* gdbserver) { this->gdbserver = gdbserver; }
+  void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
+    this->remote_bitbang = remote_bitbang;
+  }
   const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); }
   processor_t* get_core(size_t i) { return procs.at(i); }
+  unsigned nprocs() const { return procs.size(); }
+
+  // Callback for processors to let the simulation know they were reset.
+  void proc_reset(unsigned id);
 
 private:
   std::vector<std::pair<reg_t, mem_t*>> mems;
@@ -43,7 +51,6 @@ private:
   std::unique_ptr<rom_device_t> boot_rom;
   std::unique_ptr<clint_t> clint;
   bus_t bus;
-  debug_module_t debug_module;
 
   processor_t* get_core(const std::string& i);
   void step(size_t n); // step through simulation
@@ -55,7 +62,7 @@ private:
   bool debug;
   bool log;
   bool histogram_enabled; // provide a histogram of PCs
-  gdbserver_t* gdbserver;
+  remote_bitbang_t* remote_bitbang;
 
   // memory-mapped I/O routines
   char* addr_to_mem(reg_t addr);
@@ -87,7 +94,7 @@ private:
 
   friend class processor_t;
   friend class mmu_t;
-  friend class gdbserver_t;
+  friend class debug_module_t;
 
   // htif
   friend void sim_thread_main(void*);
@@ -101,6 +108,12 @@ private:
   void write_chunk(addr_t taddr, size_t len, const void* src);
   size_t chunk_align() { return 8; }
   size_t chunk_max_size() { return 8; }
+
+public:
+  // Initialize this after procs, because in debug_module_t::reset() we
+  // enumerate processors, which segfaults if procs hasn't been initialized
+  // yet.
+  debug_module_t debug_module;
 };
 
 extern volatile bool ctrlc_pressed;