X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.h;h=97e9edecb8dc08d758a4c4c46bace1127dd670c6;hb=d6fcfdebf6a893bf37670fd67203d18653df4a0e;hp=6c6e4350702d62b240a42730a20f0b3efbd8f901;hpb=aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e;p=riscv-isa-sim.git

diff --git a/riscv/sim.h b/riscv/sim.h
index 6c6e435..97e9ede 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -6,6 +6,7 @@
 #include "processor.h"
 #include "devices.h"
 #include "debug_module.h"
+#include "simif.h"
 #include <fesvr/htif.h>
 #include <fesvr/context.h>
 #include <vector>
@@ -16,7 +17,7 @@ class mmu_t;
 class remote_bitbang_t;
 
 // this class encapsulates the processors and memory in a RISC-V machine.
-class sim_t : public htif_t
+class sim_t : public htif_t, public simif_t
 {
 public:
   sim_t(const char* isa, size_t _nprocs,  bool halted, reg_t start_pc,
@@ -38,6 +39,9 @@ public:
   processor_t* get_core(size_t i) { return procs.at(i); }
   unsigned nprocs() const { return procs.size(); }
 
+  // Callback for processors to let the simulation know they were reset.
+  void proc_reset(unsigned id);
+
 private:
   std::vector<std::pair<reg_t, mem_t*>> mems;
   mmu_t* debug_mmu;  // debug port into main memory