X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fsim.h;h=d3353a1bbcfd4cebb79abcfddadd11c552b14ea1;hb=84e1ac19ed5a69224aa8c3f920e3840fbc670771;hp=8586bee2cf970ee449227af57b72f6da991c5f3b;hpb=d6fce459767509249311a120fddb21c844dc9b2c;p=riscv-isa-sim.git

diff --git a/riscv/sim.h b/riscv/sim.h
index 8586bee..d3353a1 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -13,7 +13,7 @@
 #include <memory>
 
 class mmu_t;
-class gdbserver_t;
+class remote_bitbang_t;
 
 // this class encapsulates the processors and memory in a RISC-V machine.
 class sim_t : public htif_t
@@ -29,9 +29,14 @@ public:
   void set_log(bool value);
   void set_histogram(bool value);
   void set_procs_debug(bool value);
-  void set_gdbserver(gdbserver_t* gdbserver) { this->gdbserver = gdbserver; }
+  void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
+    this->remote_bitbang = remote_bitbang;
+  }
   const char* get_dts() { return dts.c_str(); }
   processor_t* get_core(size_t i) { return procs.at(i); }
+  unsigned nprocs() const { return procs.size(); }
+
+  debug_module_t debug_module;
 
 private:
   char* mem; // main memory
@@ -42,7 +47,6 @@ private:
   std::unique_ptr<rom_device_t> boot_rom;
   std::unique_ptr<clint_t> clint;
   bus_t bus;
-  debug_module_t debug_module;
 
   processor_t* get_core(const std::string& i);
   void step(size_t n); // step through simulation
@@ -54,7 +58,7 @@ private:
   bool debug;
   bool log;
   bool histogram_enabled; // provide a histogram of PCs
-  gdbserver_t* gdbserver;
+  remote_bitbang_t* remote_bitbang;
 
   // memory-mapped I/O routines
   bool addr_is_mem(reg_t addr) {
@@ -90,7 +94,6 @@ private:
 
   friend class processor_t;
   friend class mmu_t;
-  friend class gdbserver_t;
 
   // htif
   friend void sim_thread_main(void*);