X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=setup.py;h=4f4f03381c809ab29354c14ada606ffb02e0ae9a;hb=7adf51897efdb091cce67a7db7ab2a20ebd34e35;hp=8f83c591234f4566b481f784af1c66d70fee7136;hpb=a7604013956de9733b39c21a42f4f570a3cfb37c;p=soc.git

diff --git a/setup.py b/setup.py
index 8f83c591..4f4f0338 100644
--- a/setup.py
+++ b/setup.py
@@ -9,7 +9,8 @@ NEWS = open(os.path.join(here, 'NEWS.txt')).read()
 version = '0.0.1'
 
 install_requires = [
-    'sfpy',
+#    'sfpy',
+    'ieee754fpu',
 ]
 
 test_requires = [
@@ -17,19 +18,19 @@ test_requires = [
 ]
 
 setup(
-    name='ieee754fpu',
+    name='soc',
     version=version,
-    description="A nmigen IEEE754 Floating-Point library",
+    description="A nmigen-based RISC-V Hybrid CPU / VPU / GPU",
     long_description=README + '\n\n' + NEWS,
     classifiers=[
         "Topic :: Software Development :: Libraries",
         "License :: OSI Approved :: LGPLv3+",
         "Programming Language :: Python :: 3",
     ],
-    keywords='nmigen ieee754',
+    keywords='nmigen ieee754 libre-riscv soc',
     author='Luke Kenneth Casson Leighton',
     author_email='lkcl@libre-riscv.org',
-    url='http://git.libre-riscv.org/?p=ieee754fpu',
+    url='http://git.libre-riscv.org/?p=soc',
     license='GPLv3+',
     packages=find_packages('src'),
     package_dir = {'': 'src'},