X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=shakti%2Fm_class%2Flibre_3d_gpu.mdwn;h=479ec2fed9338f5c93fe7915b63c75ebe49a72f6;hb=8ed42e7221db297105e8c14a1f7ac2b37e501596;hp=6619911639839c63c9d6e474f20ce86d8cfad541;hpb=373074c7e8294e582e14ecbf625d020ad4a6a555;p=libreriscv.git diff --git a/shakti/m_class/libre_3d_gpu.mdwn b/shakti/m_class/libre_3d_gpu.mdwn index 661991163..479ec2fed 100644 --- a/shakti/m_class/libre_3d_gpu.mdwn +++ b/shakti/m_class/libre_3d_gpu.mdwn @@ -41,7 +41,7 @@ same silicon area). * Hardware (RTL) must be licensed under BSD or MIT with no "NON-COMMERCIAL" CLAUSES. * Any proposals will be competing against Vivante GC800 (using Etnaviv driver). -* The GPU is integrated (like Mali400). So all that the GPU needs to do is write to an area of memory (framebuffer or area of the framebuffer). The SoC - which in this case has a RISC-V core and has peripherals such as the LCD controller - will take care of the rest. +* The GPU is integrated (like Mali-400). So all that the GPU needs to do is write to an area of memory (framebuffer or area of the framebuffer). The SoC - which in this case has a RISC-V core and has peripherals such as the LCD controller - will take care of the rest. * In this arcitecture, the GPU, the CPU and the peripherals are all on the same AXI4 shared memory bus. They all have access to the same shared DDR3/DDR4 RAM. So as a result the GPU will use AXI4 to write directly to the framebuffer and the rest will be handle by SoC. * The job must be done by a team that shows sufficient expertise to reduce the risk. @@ -81,7 +81,7 @@ modifying llvm for RISC-V to do the heavy-lifting instead. Then it just becomes a matter of adding vector / SIMD / parallelisation extensions to RISC-V, and adding support in LLVM for the same: ->https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html> + So if considering to base the design on RISC-V, that means turning RISC-V into a vector processor. Now, whilst Hwacha has been located (finally),