X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=shakti%2Fm_class%2Flibre_3d_gpu.mdwn;h=4c001382026c5520668c0db4cf504d457e842e96;hb=fe095ace2d0f82e9405e2699eb106d3b53e5de0c;hp=06f6fd2edbff77e45c81cd5c104ac464b854c870;hpb=8b44d3f2898a0d8e7eeb0286dab30a4e5071cbe1;p=libreriscv.git

diff --git a/shakti/m_class/libre_3d_gpu.mdwn b/shakti/m_class/libre_3d_gpu.mdwn
index 06f6fd2ed..4c0013820 100644
--- a/shakti/m_class/libre_3d_gpu.mdwn
+++ b/shakti/m_class/libre_3d_gpu.mdwn
@@ -75,7 +75,13 @@ has a *software* (LLVM) renderer:
 The general aim of this approach is *not* to have the complexity of
 transferring significant amounts of data structures to and from disparate
 cores (one Nyuzi, one RISC-V) but to STAY WITHIN THE RISC-V ARCHITECTURE
-and simply compile Mesa3D (for RISC-V), gallium3d-llvm (for RISC-V).
+and simply compile Mesa3D (for RISC-V), gallium3d-llvm (for RISC-V),
+modifying llvm for RISC-V to do the heavy-lifting instead.
+
+Then it just becomes a matter of adding vector / SIMD / parallelisation
+extensions to RISC-V, and adding support in LLVM for the same:
+
+<https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html>
 
 So if considering to base the design on RISC-V, that means turning RISC-V
 into a vector processor. Now, whilst Hwacha has been located (finally),