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diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index 4fb00249b..536afd6e3 100644
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -79,6 +79,54 @@
 }
 
 
+\frame{\frametitle{Does what we want already exist? Surely this is nonsense!}
+ \begin{center}
+  \includegraphics[height=2.4in]{nolibresocs.jpg}\\
+  {\bf Analysis of SoCs over the past 7+ years (answer: no)}
+ \end{center}
+}
+
+
+\frame{\frametitle{Breakdown of non-existence of fully-Libre SoCs}
+
+ \begin{itemize}
+   \item {\bf iMX6}: Libre bootable, Vivante 3D GPU (libre etnaviv)
+            but proprietary VPU (and a power-hungry Cortex A9)
+	\item {\bf Allwinner SoCs}: mostly Libre bootable,
+	      VPU reverse engineered; GPU: MALI or PowerVR (i.e. proprietary)
+	\item {\bf Rockchip SoCs}: good but using MALI or PowerVR.
+	\item {\bf TI OMAP}: good but using PowerVR.  and expensive.
+	\item {\bf Samsung}: good but using MALI.
+	\item {\bf Ingenic jz4775}: GREAT! performance
+		  sucks (1ghz MIPS32).
+	\item {\bf Broadcom SoCs}: Cartelled. and boots from the GPU
+  \end{itemize}
+  {\it Basically there does not exist one single commercial SoC that
+   provides full source code for all functions (CPU, GPU, VPU)
+   with modern performance. Which is kinda bizarre if you think about it}
+}
+
+
+\frame{\frametitle{What would a good (Libre) boring, mundane SoC have?}
+
+ \begin{itemize}
+   \item Cover a lot of different scenarios (embedded, tablets, industrial,
+         netbooks, crypto-currency mining).
+	\item Decent performance with high efficiency.  RISC-V: 40 \%
+		  more efficient than ARM / Intel.  Shakti a good
+	      candidate: 2.5ghz and 120mW per core @ 22nm.
+	\item 1080p video: y'all gotta watch cute kittens on youtube, right?
+	\item 3D GPU: y'all gotta play Angri Burds, right? (or Minecraft)
+	\item No spying back-door co-processors (to steal crypto-wallets)
+	\item No Spectres, no Meltdowns.
+  \end{itemize}
+  {\it Basically quite boring and mundane.  No Monster Performance,
+   no AI stuff, no special sauce. Just a plain-old SoC,
+   40\% more power efficient than ARM/Intel,
+   and not spying on end-users, that's all}
+}
+
+
 \frame{\frametitle{How on earth does an ethical Libre SoC make money???}
 
  \begin{itemize}
@@ -89,10 +137,13 @@
    \item Without a desirable product or customer(s): err... you don't.\\
 	     (cf: definition of Business)
    \item By not having high NREs (leveraging back-to-back deals,
-	     and helping others fulfil their needs)
+	     and helping others fulfil their needs and goals)
   \end{itemize}
   {\it Detachment from the goal also helps. If someone else makes this
-   product then GREAT! I can go do something else}
+   product then GREAT! I can go do something else}\\
+   \vspace{4pt}
+  {\bf Main point: please do not automatically assume Ethical and Libre is
+   non-commercial. It's not nice, and it's not helping }
 
 }
 
@@ -102,11 +153,11 @@
    \item Customer entrapment (through proprietary software).\\
          Strong business case for not entrapping customers:\\
 	     https://tinyurl.com/most-productive-meeting-ever
-   \item Funding, endorsing, empowering or otherwise supporting
-	      unethical Companies, Organisations and Individuals.\\
+   \item Funding, endorsing, supporting or empowering unethical
+         Companies, Organisations, Cartels and Individuals.\\
 	     (cf: definition of an ethical act).
 	\item Being totally inflexible / unrealistic.  Goals have
-	     to be met: it's no good being an idiot about that. If
+	     to be met: it's no good being an idiot about that. e.g. if
 	     a Libre 3D GPU really can't be made, use Vivante GC800
 	     (with etnaviv).
   \end{itemize}
@@ -124,10 +175,11 @@
  \end{center}
 }
 
+
 \frame{\frametitle{Hardware / Development Complexity Comparison}
 
  \begin{itemize}
-   \item {\bf Server}: relatively easy. PCIe, RapidIO, XAUI, SATA, (1/10) GbE,
+   \item {\bf Server}: relatively easy. PCIe, RapidIO, XAUI, SATA, GbE, 10GE,
 		 DDR3/4 (or HMC) etc. etc. No multiplexing: all interfaces dedicated
 		 and high-speed differential pairs.
    \item {\bf Desktop}: really just a variant of Server.
@@ -144,6 +196,88 @@
 }
 
 
+\frame{\frametitle{Proprietary vs Libre-licensed Interface HDL}
+
+ \begin{itemize}
+   \item DDR3/4: challenging! \$1m for single-use, single instance.\\
+         Symbiotic EDA: \$600k for PHY; CERN developed a Controller\\
+         http://libre-riscv.org/shakti/m\_class/DDR/
+   \item HyperRAM (JEDEC xSPI): lower risk than DDR3/4\\
+	   http://libre-riscv.org/shakti/m\_class/HyperRAM/
+   \item RGMII: several available (saves \$50k)\\
+	   http://libre-riscv.org/shakti/m\_class/RGMII/
+   \item UART, SPI, I2C, PWM, SD/MMC: all libre (except eMMC).
+   \item Shakti Group has FlexBus, QuadSPI, SRAM, many more.
+   \item RGB/TTL: R. Herveille (SSD2828, SN75LVDS83b, TFP410a)
+  \end{itemize}
+  {\it Basically there's no compelling reason to spend vast sums
+   on proprietary HDL.  Sorry Cadence / Mentor / Synopsis / whoever}
+}
+
+
+\frame{\frametitle{Challenging Stuff [1] - Memory Interfaces}
+
+ \begin{itemize}
+   \item DDR3/4 PHYs are analog and very high speed.
+		   Impedance training.  Extreme timing tolerances on parallel buses.\\
+		   No surprise they cost USD \$1m and above.
+   \item Symbiotic EDA will do (Libre) PHY layout for USD \$300k,
+	     time to completion for chosen geometry: 8-12 months.
+  \end{itemize}
+   {\it Silicon-proven but still risky.  What are the alternatives?}
+   \vspace{4pt}
+ \begin{itemize}
+   \item 133mhz 32-bit SDRAM (um...) maybe even FlexBus?
+   \item HyperRAM (aka JEDEC xSPI) 8-bit SPI 166mhz or DDR-300.\\
+	   300mbyte/sec for only 13 wires, not bad!  (We'll take several)\\
+	   http://libre-riscv.org/shakti/m\_class/HyperRAM/
+   \item HMC: insanely fast, very low power.  OpenHMC (LGPL)
+	   https://opencores.org/project/openhmc
+  \end{itemize}
+}
+
+
+\frame{\frametitle{Challenging Stuff [2] - Video Decode Engine}
+
+ \begin{itemize}
+   \item Richard Herveille's Video Core Blocks\\
+    	    https://opencores.org/project/video\_systems
+   \item Symbiotic EDA MP4 decoder in FPGA
+   \item H.264 seems to have been done...\\
+         https://github.com/adsc-hls/synthesizable\_h264
+   \item Really needs SIMD (or better, not-SIMD)\\
+         {http://libre-riscv.org/simple\_v\_extension/}
+   \item Definitely needs xBitManip (parallelised by Simple-V)\\
+         https://github.com/cliffordwolf/xbitmanip
+  \end{itemize}
+   {\it SIMD is insane. $O(N^6)$ opcode proliferation.  See\\
+     https://www.sigarch.org/simd-instructions-considered-harmful/ \\
+     (1): P-Ext designed for Audio. (2): Investigate RI5CY's SIMD
+   }
+}
+
+
+\frame{\frametitle{Challenging Stuff [3] - Libre 3D GPU.  Sigh.}
+
+ \begin{itemize}
+   \item Actual requirements quite modest: 30MP/s 100MT/s 5GFLOPS
+         but power/area is crucial ($2mm^2$ @ 40nm)
+   \item Nyuzi, MIAOW, GPLGPU (Number Nine), OGP.
+   \item Nyuzi based on Larrabee. Jeff Bush really helpful.
+   \item MIAOW is an OpenCL engine.  GPLGPU is fixed-function
+   \item Nyuzi lessons: Software-only rendering not enough.
+	     Getting through L1 cache takes most power. Fixed functions
+	     such as parallel FP-Quad to ARGB Pixel, and Z-Buffer
+	     needed.
+   \item Fallback is GC800 (\$250k) {\it contact me if you can do better!}
+  \end{itemize}
+   {\it Jacob Bachmeyer's Cache-control proposal turns L1 Cache into
+   scratchpad RAM.  RVV is just too heavy (sorry!), Simple-V much
+   more light-weight and flexible.
+   }
+}
+
+
 \frame{\frametitle{TODO}
 
  \begin{itemize}