X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=simple_v_extension%2Fv_comparative_analysis.mdwn;h=9736bdf74dbaf85ba6aba46f1df9d714abac9527;hb=HEAD;hp=5a955d2e90ef18f8dfe2494e396220002f342023;hpb=0a9cd42f66c016bd175953cce0b07c3baa1329e2;p=libreriscv.git

diff --git a/simple_v_extension/v_comparative_analysis.mdwn b/simple_v_extension/v_comparative_analysis.mdwn
index 5a955d2e9..9736bdf74 100644
--- a/simple_v_extension/v_comparative_analysis.mdwn
+++ b/simple_v_extension/v_comparative_analysis.mdwn
@@ -443,85 +443,87 @@ modes.
 # TODO: instructions V-Ext duplication analysis <a name="duplication_analysis">
 
 This is partly speculative due to lack of access to an up-to-date
-V-Ext Spec (V2.3-draft RVV 0.4-Draft at the time of writing).  However
-basin an analysis instead on Hwacha, a cursory examination shows over
-an **85%** duplication of V-Ext operand-related instructions when
-compared to Simple-V on a standard RG64G base.   Even Vector Fetch
-is analogous to "zero-overhead loop".
+V-Ext Spec (V2.3-draft RVV 0.4-Draft at the time of writing).  
+A cursory examination shows an **85%** duplication of V-Ext
+operand-related instructions when compared to a standard RG64G base,
+and a **95%** duplication of arithmetic and floating-point operations.
 
 Exceptions are:
 
-* Vector Indexed Memory Instructions (non-contiguous)
-* Vector Atomic Memory Instructions.
-* Some of the Vector Misc ops: VEIDX, VFIRST, VCLASS, VPOPC
-  and potentially more.
-* Consensual Jump
+* The Vector Misc ops: VEIDX, VFIRST, VPOPC
+  and potentially more (9 control-related instructions)
+* VCLIP and VCLIPI (the only 2 opcodes not duplicated out of 47
+  total arithmetic / floating-point operations)
 
 Table of RV32V Instructions
 
-| RV32V      | RV Equivalent (FP)   | RV Equivalent (Int) | Notes |
-| -----      | --- | |   |
-| VADD       | FADD    | ADD |   |
-| VSUB       | FSUB    | SUB |   |
-| VSL        |     | SLL |   |
-| VSR        |     | SRL |   |
-| VAND       |     | AND |   |
-| VOR        |     | OR |   |
-| VXOR       |     | XOR |   |
-| VSEQ       | FEQ | BEQ | {1} |
-| VSNE       | !FEQ | BNE | {1} |
-| VSLT       | FLT    | BLT | {1} |
-| VSGE       | !FLE | BGE | {1} |
-| VCLIP      |     | |   |
-| VCVT       | FCVT    | |   |
-| VMPOP      |     | |   |
-| VMFIRST    |     | |   |
-| VEXTRACT   |     | |   |
-| VINSERT    |     | |   |
-| VMERGE     |     | |   |
-| VSELECT    |     | |   |
-| VSLIDE     |     | |   |
-| VDIV       | FDIV    | DIV |   |
-| VREM       |     | REM |   |
-| VMUL       | FMUL    | MUL |   |
-| VMULH      |     | |   |
-| VMIN       | FMIN    | |   |
-| VMAX       | FMUX    | |   |
-| VSGNJ      | FSGNJ    | |   |
-| VSGNJN     | FSGNJN    | |   |
-| VSGNJX     | FSNGJX    | |   |
-| VSQRT      | FSQRT    | |   |
-| VCLASS     |     | |   |
-| VPOPC      |     | |   |
-| VADDI      |     | ADDI |   |
-| VSLI       |     | SLI |   |
-| VSRI       |     | SRI |   |
-| VANDI      |     | ANDI |   |
-| VORI       |     | ORI |   |
-| VXORI      |     | XORI |   |
-| VCLIPI     |     | |   |
-| VMADD      | FMADD    | |   |
-| VMSUB      | FMSUB    | |   |
-| VNMADD     | FNMSUB    | |   |
-| VNMSUB     | FNMADD    | |   |
-| VLD        | FLD    | LD |   |
-| VLDS       |     | LW |   |
-| VLDX       |     | LWU |   |
-| VST        | FST    | ST |   |
-| VSTS       |     | |   |
-| VSTX       |     | |   |
-| VAMOSWAP   |     | AMOSWAP |   |
-| VAMOADD    |     | AMOADD |   |
-| VAMOAND    |     | AMOAND |   |
-| VAMOOR     |     | AMOOR |   |
-| VAMOXOR    |     | AMOXOR |   |
-| VAMOMIN    |     | AMOMIN |   |
-| VAMOMAX    |     | AMOMAX |   |
+| RV32V      | RV Std (FP) | RV Std (Int) | Notes |
+| -----      | ---      |         |   |
+| VADD       | FADD     | ADD     |   |
+| VSUB       | FSUB     | SUB     |   |
+| VSL        |          | SLL     |   |
+| VSR        |          | SRL     |   |
+| VAND       |          | AND     |   |
+| VOR        |          | OR      |   |
+| VXOR       |          | XOR     |   |
+| VSEQ       | FEQ      | BEQ     | (1) |
+| VSNE       | !FEQ     | BNE     | (1) |
+| VSLT       | FLT      | BLT     | (1) |
+| VSGE       | !FLE     | BGE     | (1) |
+| VCLIP      |          |         |   |
+| VCVT       | FCVT     |         |   |
+| VMPOP      |          |         |   |
+| VMFIRST    |          |         |   |
+| VEXTRACT   |          |         |   |
+| VINSERT    |          |         |   |
+| VMERGE     |          |         |   |
+| VSELECT    |          |         |   |
+| VSLIDE     |          |         |   |
+| VDIV       | FDIV     | DIV     |   |
+| VREM       |          | REM     |   |
+| VMUL       | FMUL     | MUL     |   |
+| VMULH      |          | MULH    |   |
+| VMIN       | FMIN     |         |   |
+| VMAX       | FMUX     |         |   |
+| VSGNJ      | FSGNJ    |         |   |
+| VSGNJN     | FSGNJN   |         |   |
+| VSGNJX     | FSNGJX   |         |   |
+| VSQRT      | FSQRT    |         |   |
+| VCLASS     | FCLASS   |         |   |
+| VPOPC      |          |         |   |
+| VADDI      |          | ADDI    |   |
+| VSLI       |          | SLI     |   |
+| VSRI       |          | SRI     |   |
+| VANDI      |          | ANDI    |   |
+| VORI       |          | ORI     |   |
+| VXORI      |          | XORI    |   |
+| VCLIPI     |          |         |   |
+| VMADD      | FMADD    |         |   |
+| VMSUB      | FMSUB    |         |   |
+| VNMADD     | FNMSUB   |         |   |
+| VNMSUB     | FNMADD   |         |   |
+| VLD        | FLD      | LD      |   |
+| VLDS       | FLD      | LD      | (2)  |
+| VLDX       | FLD      | LD      | (3)  |
+| VST        | FST      | ST      |   |
+| VSTS       | FST      | ST      | (2)  |
+| VSTX       | FST      | ST      | (3)  |
+| VAMOSWAP   |          | AMOSWAP |   |
+| VAMOADD    |          | AMOADD  |   |
+| VAMOAND    |          | AMOAND  |   |
+| VAMOOR     |          | AMOOR   |   |
+| VAMOXOR    |          | AMOXOR  |   |
+| VAMOMIN    |          | AMOMIN  |   |
+| VAMOMAX    |          | AMOMAX  |   |
 
 Notes:
 
-* {1} retro-fit predication variants into branch instructions (base and C),
+* (1) retro-fit predication variants into branch instructions (base and C),
   decoding triggered by CSR bit marking register as "Vector type".
+* (2) retro-fit LOAD/STORE constant-stride by reinterpreting one bit of
+  immediate-offset when register arguments are detected as being vectorised
+* (3) retro-fit LOAD/STORE indexed-stride through detection of address
+  register argument being vectorised
 
 # TODO: sort